0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2020 Gateworks Corporation
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/linux-event-codes.h>
0010 #include <dt-bindings/leds/common.h>
0011 #include <dt-bindings/phy/phy-imx8-pcie.h>
0012
0013 #include "imx8mm.dtsi"
0014
0015 / {
0016 model = "Gateworks Venice GW7901 i.MX8MM board";
0017 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
0018
0019 aliases {
0020 ethernet0 = &fec1;
0021 ethernet1 = &lan1;
0022 ethernet2 = &lan2;
0023 ethernet3 = &lan3;
0024 ethernet4 = &lan4;
0025 usb0 = &usbotg1;
0026 usb1 = &usbotg2;
0027 };
0028
0029 chosen {
0030 stdout-path = &uart2;
0031 };
0032
0033 memory@40000000 {
0034 device_type = "memory";
0035 reg = <0x0 0x40000000 0 0x80000000>;
0036 };
0037
0038 gpio-keys {
0039 compatible = "gpio-keys";
0040
0041 key-user-pb {
0042 label = "user_pb";
0043 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
0044 linux,code = <BTN_0>;
0045 };
0046
0047 key-user-pb1x {
0048 label = "user_pb1x";
0049 linux,code = <BTN_1>;
0050 interrupt-parent = <&gsc>;
0051 interrupts = <0>;
0052 };
0053
0054 key-erased {
0055 label = "key_erased";
0056 linux,code = <BTN_2>;
0057 interrupt-parent = <&gsc>;
0058 interrupts = <1>;
0059 };
0060
0061 key-eeprom-wp {
0062 label = "eeprom_wp";
0063 linux,code = <BTN_3>;
0064 interrupt-parent = <&gsc>;
0065 interrupts = <2>;
0066 };
0067
0068 key-tamper {
0069 label = "tamper";
0070 linux,code = <BTN_4>;
0071 interrupt-parent = <&gsc>;
0072 interrupts = <5>;
0073 };
0074
0075 switch-hold {
0076 label = "switch_hold";
0077 linux,code = <BTN_5>;
0078 interrupt-parent = <&gsc>;
0079 interrupts = <7>;
0080 };
0081 };
0082
0083 led-controller {
0084 compatible = "gpio-leds";
0085
0086 led-0 {
0087 function = LED_FUNCTION_STATUS;
0088 color = <LED_COLOR_ID_RED>;
0089 label = "led01_red";
0090 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
0091 default-state = "off";
0092 };
0093
0094 led-1 {
0095 function = LED_FUNCTION_STATUS;
0096 color = <LED_COLOR_ID_GREEN>;
0097 label = "led01_grn";
0098 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
0099 default-state = "off";
0100 };
0101
0102 led-2 {
0103 function = LED_FUNCTION_STATUS;
0104 color = <LED_COLOR_ID_RED>;
0105 label = "led02_red";
0106 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
0107 default-state = "off";
0108 };
0109
0110 led-3 {
0111 function = LED_FUNCTION_STATUS;
0112 color = <LED_COLOR_ID_GREEN>;
0113 label = "led02_grn";
0114 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
0115 default-state = "off";
0116 };
0117
0118 led-4 {
0119 function = LED_FUNCTION_STATUS;
0120 color = <LED_COLOR_ID_RED>;
0121 label = "led03_red";
0122 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
0123 default-state = "off";
0124 };
0125
0126 led-5 {
0127 function = LED_FUNCTION_STATUS;
0128 color = <LED_COLOR_ID_GREEN>;
0129 label = "led03_grn";
0130 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
0131 default-state = "off";
0132 };
0133
0134 led-6 {
0135 function = LED_FUNCTION_STATUS;
0136 color = <LED_COLOR_ID_RED>;
0137 label = "led04_red";
0138 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
0139 default-state = "off";
0140 };
0141
0142 led-7 {
0143 function = LED_FUNCTION_STATUS;
0144 color = <LED_COLOR_ID_GREEN>;
0145 label = "led04_grn";
0146 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
0147 default-state = "off";
0148 };
0149
0150 led-8 {
0151 function = LED_FUNCTION_STATUS;
0152 color = <LED_COLOR_ID_RED>;
0153 label = "led05_red";
0154 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
0155 default-state = "off";
0156 };
0157
0158 led-9 {
0159 function = LED_FUNCTION_STATUS;
0160 color = <LED_COLOR_ID_GREEN>;
0161 label = "led05_grn";
0162 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
0163 default-state = "off";
0164 };
0165
0166 led-a {
0167 function = LED_FUNCTION_STATUS;
0168 color = <LED_COLOR_ID_RED>;
0169 label = "led06_red";
0170 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
0171 default-state = "off";
0172 };
0173
0174 led-b {
0175 function = LED_FUNCTION_STATUS;
0176 color = <LED_COLOR_ID_GREEN>;
0177 label = "led06_grn";
0178 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
0179 default-state = "off";
0180 };
0181 };
0182
0183 pcie0_refclk: pcie0-refclk {
0184 compatible = "fixed-clock";
0185 #clock-cells = <0>;
0186 clock-frequency = <100000000>;
0187 };
0188
0189 reg_3p3v: regulator-3p3v {
0190 compatible = "regulator-fixed";
0191 regulator-name = "3P3V";
0192 regulator-min-microvolt = <3300000>;
0193 regulator-max-microvolt = <3300000>;
0194 };
0195
0196 regulator-ioexp {
0197 pinctrl-names = "default";
0198 pinctrl-0 = <&pinctrl_reg_ioexp>;
0199 compatible = "regulator-fixed";
0200 regulator-name = "ioexp";
0201 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
0202 enable-active-high;
0203 startup-delay-us = <100>;
0204 regulator-min-microvolt = <3300000>;
0205 regulator-max-microvolt = <3300000>;
0206 regulator-always-on;
0207 };
0208
0209 regulator-isouart {
0210 pinctrl-names = "default";
0211 pinctrl-0 = <&pinctrl_reg_isouart>;
0212 compatible = "regulator-fixed";
0213 regulator-name = "iso_uart";
0214 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
0215 startup-delay-us = <100>;
0216 regulator-min-microvolt = <3300000>;
0217 regulator-max-microvolt = <3300000>;
0218 regulator-always-on;
0219 };
0220
0221 reg_usb2_vbus: regulator-usb2 {
0222 pinctrl-names = "default";
0223 pinctrl-0 = <&pinctrl_reg_usb2>;
0224 compatible = "regulator-fixed";
0225 regulator-name = "usb_usb2_vbus";
0226 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
0227 enable-active-high;
0228 regulator-min-microvolt = <5000000>;
0229 regulator-max-microvolt = <5000000>;
0230 };
0231
0232 reg_wifi: regulator-wifi {
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&pinctrl_reg_wl>;
0235 compatible = "regulator-fixed";
0236 regulator-name = "wifi";
0237 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
0238 enable-active-high;
0239 startup-delay-us = <100>;
0240 regulator-min-microvolt = <3300000>;
0241 regulator-max-microvolt = <3300000>;
0242 };
0243 };
0244
0245 &ddrc {
0246 operating-points-v2 = <&ddrc_opp_table>;
0247
0248 ddrc_opp_table: opp-table {
0249 compatible = "operating-points-v2";
0250
0251 opp-25M {
0252 opp-hz = /bits/ 64 <25000000>;
0253 };
0254
0255 opp-100M {
0256 opp-hz = /bits/ 64 <100000000>;
0257 };
0258
0259 opp-750M {
0260 opp-hz = /bits/ 64 <750000000>;
0261 };
0262 };
0263 };
0264
0265 &disp_blk_ctrl {
0266 status = "disabled";
0267 };
0268
0269 &ecspi1 {
0270 pinctrl-names = "default";
0271 pinctrl-0 = <&pinctrl_spi1>;
0272 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0273 status = "okay";
0274
0275 flash@0 {
0276 compatible = "jedec,spi-nor";
0277 reg = <0>;
0278 spi-max-frequency = <40000000>;
0279 status = "okay";
0280 };
0281 };
0282
0283 &fec1 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_fec1>;
0286 phy-mode = "rgmii-id";
0287 local-mac-address = [00 00 00 00 00 00];
0288 status = "okay";
0289
0290 fixed-link {
0291 speed = <1000>;
0292 full-duplex;
0293 };
0294 };
0295
0296 &gpio1 {
0297 gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
0298 "", "uart1_rs232#", "dig1_in", "dig1_out",
0299 "", "", "", "", "", "", "", "",
0300 "", "", "", "", "", "", "", "",
0301 "", "", "", "", "", "", "", "";
0302 };
0303
0304 &gpio4 {
0305 gpio-line-names = "", "", "", "",
0306 "", "", "uart3_rs232#", "uart3_rs422#",
0307 "uart3_rs485#", "", "", "", "", "", "", "",
0308 "", "", "", "", "", "", "", "",
0309 "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
0310 };
0311
0312 &gpio5 {
0313 gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
0314 "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
0315 "", "", "", "", "", "", "", "",
0316 "", "", "", "", "", "", "", "";
0317 };
0318
0319 &gpu_2d {
0320 status = "disabled";
0321 };
0322
0323 &gpu_3d {
0324 status = "disabled";
0325 };
0326
0327 &i2c1 {
0328 clock-frequency = <100000>;
0329 pinctrl-names = "default";
0330 pinctrl-0 = <&pinctrl_i2c1>;
0331 status = "okay";
0332
0333 gsc: gsc@20 {
0334 compatible = "gw,gsc";
0335 reg = <0x20>;
0336 pinctrl-0 = <&pinctrl_gsc>;
0337 interrupt-parent = <&gpio4>;
0338 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
0339 interrupt-controller;
0340 #interrupt-cells = <1>;
0341
0342 adc {
0343 compatible = "gw,gsc-adc";
0344 #address-cells = <1>;
0345 #size-cells = <0>;
0346
0347 channel@6 {
0348 gw,mode = <0>;
0349 reg = <0x06>;
0350 label = "temp";
0351 };
0352
0353 channel@8 {
0354 gw,mode = <1>;
0355 reg = <0x08>;
0356 label = "vdd_bat";
0357 };
0358
0359 channel@82 {
0360 gw,mode = <2>;
0361 reg = <0x82>;
0362 label = "vin_aux1";
0363 gw,voltage-divider-ohms = <22100 1000>;
0364 };
0365
0366 channel@84 {
0367 gw,mode = <2>;
0368 reg = <0x84>;
0369 label = "vin_aux2";
0370 gw,voltage-divider-ohms = <22100 1000>;
0371 };
0372
0373 channel@86 {
0374 gw,mode = <2>;
0375 reg = <0x86>;
0376 label = "vdd_vin";
0377 gw,voltage-divider-ohms = <22100 1000>;
0378 };
0379
0380 channel@88 {
0381 gw,mode = <2>;
0382 reg = <0x88>;
0383 label = "vdd_3p3";
0384 gw,voltage-divider-ohms = <10000 10000>;
0385 };
0386
0387 channel@8c {
0388 gw,mode = <2>;
0389 reg = <0x8c>;
0390 label = "vdd_2p5";
0391 gw,voltage-divider-ohms = <10000 10000>;
0392 };
0393
0394 channel@8e {
0395 gw,mode = <2>;
0396 reg = <0x8e>;
0397 label = "vdd_0p95";
0398 };
0399
0400 channel@90 {
0401 gw,mode = <2>;
0402 reg = <0x90>;
0403 label = "vdd_soc";
0404 };
0405
0406 channel@92 {
0407 gw,mode = <2>;
0408 reg = <0x92>;
0409 label = "vdd_arm";
0410 };
0411
0412 channel@98 {
0413 gw,mode = <2>;
0414 reg = <0x98>;
0415 label = "vdd_1p8";
0416 };
0417
0418 channel@9a {
0419 gw,mode = <2>;
0420 reg = <0x9a>;
0421 label = "vdd_1p2";
0422 };
0423
0424 channel@9c {
0425 gw,mode = <2>;
0426 reg = <0x9c>;
0427 label = "vdd_dram";
0428 };
0429
0430 channel@a2 {
0431 gw,mode = <2>;
0432 reg = <0xa2>;
0433 label = "vdd_gsc";
0434 gw,voltage-divider-ohms = <10000 10000>;
0435 };
0436 };
0437 };
0438
0439 gpio: gpio@23 {
0440 compatible = "nxp,pca9555";
0441 reg = <0x23>;
0442 gpio-controller;
0443 #gpio-cells = <2>;
0444 interrupt-parent = <&gsc>;
0445 interrupts = <4>;
0446 };
0447
0448 eeprom@50 {
0449 compatible = "atmel,24c02";
0450 reg = <0x50>;
0451 pagesize = <16>;
0452 };
0453
0454 eeprom@51 {
0455 compatible = "atmel,24c02";
0456 reg = <0x51>;
0457 pagesize = <16>;
0458 };
0459
0460 eeprom@52 {
0461 compatible = "atmel,24c02";
0462 reg = <0x52>;
0463 pagesize = <16>;
0464 };
0465
0466 eeprom@53 {
0467 compatible = "atmel,24c02";
0468 reg = <0x53>;
0469 pagesize = <16>;
0470 };
0471
0472 rtc@68 {
0473 compatible = "dallas,ds1672";
0474 reg = <0x68>;
0475 };
0476 };
0477
0478 &i2c2 {
0479 clock-frequency = <400000>;
0480 pinctrl-names = "default";
0481 pinctrl-0 = <&pinctrl_i2c2>;
0482 status = "okay";
0483
0484 pmic@4b {
0485 compatible = "rohm,bd71847";
0486 reg = <0x4b>;
0487 pinctrl-names = "default";
0488 pinctrl-0 = <&pinctrl_pmic>;
0489 interrupt-parent = <&gpio3>;
0490 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
0491 rohm,reset-snvs-powered;
0492 #clock-cells = <0>;
0493 clocks = <&osc_32k 0>;
0494 clock-output-names = "clk-32k-out";
0495
0496 regulators {
0497 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
0498 BUCK1 {
0499 regulator-name = "buck1";
0500 regulator-min-microvolt = <700000>;
0501 regulator-max-microvolt = <1300000>;
0502 regulator-boot-on;
0503 regulator-always-on;
0504 regulator-ramp-delay = <1250>;
0505 };
0506
0507 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
0508 BUCK2 {
0509 regulator-name = "buck2";
0510 regulator-min-microvolt = <700000>;
0511 regulator-max-microvolt = <1300000>;
0512 regulator-boot-on;
0513 regulator-always-on;
0514 regulator-ramp-delay = <1250>;
0515 rohm,dvs-run-voltage = <1000000>;
0516 rohm,dvs-idle-voltage = <900000>;
0517 };
0518
0519 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
0520 BUCK3 {
0521 regulator-name = "buck3";
0522 regulator-min-microvolt = <700000>;
0523 regulator-max-microvolt = <1350000>;
0524 regulator-boot-on;
0525 regulator-always-on;
0526 };
0527
0528 /* vdd_3p3 */
0529 BUCK4 {
0530 regulator-name = "buck4";
0531 regulator-min-microvolt = <3000000>;
0532 regulator-max-microvolt = <3300000>;
0533 regulator-boot-on;
0534 regulator-always-on;
0535 };
0536
0537 /* vdd_1p8 */
0538 BUCK5 {
0539 regulator-name = "buck5";
0540 regulator-min-microvolt = <1605000>;
0541 regulator-max-microvolt = <1995000>;
0542 regulator-boot-on;
0543 regulator-always-on;
0544 };
0545
0546 /* vdd_dram */
0547 BUCK6 {
0548 regulator-name = "buck6";
0549 regulator-min-microvolt = <800000>;
0550 regulator-max-microvolt = <1400000>;
0551 regulator-boot-on;
0552 regulator-always-on;
0553 };
0554
0555 /* nvcc_snvs_1p8 */
0556 LDO1 {
0557 regulator-name = "ldo1";
0558 regulator-min-microvolt = <1600000>;
0559 regulator-max-microvolt = <1900000>;
0560 regulator-boot-on;
0561 regulator-always-on;
0562 };
0563
0564 /* vdd_snvs_0p8 */
0565 LDO2 {
0566 regulator-name = "ldo2";
0567 regulator-min-microvolt = <800000>;
0568 regulator-max-microvolt = <900000>;
0569 regulator-boot-on;
0570 regulator-always-on;
0571 };
0572
0573 /* vdda_1p8 */
0574 LDO3 {
0575 regulator-name = "ldo3";
0576 regulator-min-microvolt = <1800000>;
0577 regulator-max-microvolt = <3300000>;
0578 regulator-boot-on;
0579 regulator-always-on;
0580 };
0581
0582 LDO4 {
0583 regulator-name = "ldo4";
0584 regulator-min-microvolt = <900000>;
0585 regulator-max-microvolt = <1800000>;
0586 regulator-boot-on;
0587 regulator-always-on;
0588 };
0589
0590 LDO6 {
0591 regulator-name = "ldo6";
0592 regulator-min-microvolt = <900000>;
0593 regulator-max-microvolt = <1800000>;
0594 regulator-boot-on;
0595 regulator-always-on;
0596 };
0597 };
0598 };
0599 };
0600
0601 &i2c3 {
0602 clock-frequency = <400000>;
0603 pinctrl-names = "default";
0604 pinctrl-0 = <&pinctrl_i2c3>;
0605 status = "okay";
0606
0607 leds_gpio: gpio@20 {
0608 compatible = "nxp,pca9555";
0609 reg = <0x20>;
0610 gpio-controller;
0611 #gpio-cells = <2>;
0612 };
0613
0614 switch: switch@5f {
0615 compatible = "microchip,ksz9897";
0616 reg = <0x5f>;
0617 pinctrl-0 = <&pinctrl_ksz>;
0618 interrupt-parent = <&gpio4>;
0619 interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
0620 phy-mode = "rgmii-id";
0621
0622 ports {
0623 #address-cells = <1>;
0624 #size-cells = <0>;
0625
0626 lan1: port@0 {
0627 reg = <0>;
0628 label = "lan1";
0629 phy-mode = "internal";
0630 local-mac-address = [00 00 00 00 00 00];
0631 };
0632
0633 lan2: port@1 {
0634 reg = <1>;
0635 label = "lan2";
0636 phy-mode = "internal";
0637 local-mac-address = [00 00 00 00 00 00];
0638 };
0639
0640 lan3: port@2 {
0641 reg = <2>;
0642 label = "lan3";
0643 phy-mode = "internal";
0644 local-mac-address = [00 00 00 00 00 00];
0645 };
0646
0647 lan4: port@3 {
0648 reg = <3>;
0649 label = "lan4";
0650 phy-mode = "internal";
0651 local-mac-address = [00 00 00 00 00 00];
0652 };
0653
0654 port@5 {
0655 reg = <5>;
0656 label = "cpu";
0657 ethernet = <&fec1>;
0658 phy-mode = "rgmii-id";
0659
0660 fixed-link {
0661 speed = <1000>;
0662 full-duplex;
0663 };
0664 };
0665 };
0666 };
0667
0668 crypto@60 {
0669 compatible = "atmel,atecc508a";
0670 reg = <0x60>;
0671 };
0672 };
0673
0674 &i2c4 {
0675 clock-frequency = <400000>;
0676 pinctrl-names = "default";
0677 pinctrl-0 = <&pinctrl_i2c4>;
0678 status = "okay";
0679 };
0680
0681 &pcie_phy {
0682 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0683 fsl,clkreq-unsupported;
0684 clocks = <&pcie0_refclk>;
0685 clock-names = "ref";
0686 status = "okay";
0687 };
0688
0689 &pcie0 {
0690 pinctrl-names = "default";
0691 pinctrl-0 = <&pinctrl_pcie0>;
0692 reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
0693 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0694 <&pcie0_refclk>;
0695 clock-names = "pcie", "pcie_aux", "pcie_bus";
0696 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0697 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0698 assigned-clock-rates = <10000000>, <250000000>;
0699 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0700 <&clk IMX8MM_SYS_PLL2_250M>;
0701 status = "okay";
0702 };
0703
0704 &pgc_gpu {
0705 status = "disabled";
0706 };
0707
0708 &pgc_gpumix {
0709 status = "disabled";
0710 };
0711
0712 &pgc_mipi {
0713 status = "disabled";
0714 };
0715
0716 &uart1 {
0717 pinctrl-names = "default";
0718 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
0719 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
0720 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
0721 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
0722 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
0723 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
0724 uart-has-rtscts;
0725 status = "okay";
0726 };
0727
0728 /* console */
0729 &uart2 {
0730 pinctrl-names = "default";
0731 pinctrl-0 = <&pinctrl_uart2>;
0732 status = "okay";
0733 };
0734
0735 &uart3 {
0736 pinctrl-names = "default";
0737 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
0738 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
0739 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
0740 uart-has-rtscts;
0741 status = "okay";
0742 };
0743
0744 &uart4 {
0745 pinctrl-names = "default";
0746 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
0747 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
0748 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
0749 uart-has-rtscts;
0750 status = "okay";
0751 };
0752
0753 &usbotg1 {
0754 dr_mode = "host";
0755 disable-over-current;
0756 status = "okay";
0757 };
0758
0759 &usbotg2 {
0760 dr_mode = "host";
0761 vbus-supply = <®_usb2_vbus>;
0762 status = "okay";
0763 };
0764
0765 /* SDIO WiFi */
0766 &usdhc1 {
0767 pinctrl-names = "default";
0768 pinctrl-0 = <&pinctrl_usdhc1>;
0769 bus-width = <4>;
0770 non-removable;
0771 vmmc-supply = <®_wifi>;
0772 status = "okay";
0773 };
0774
0775 /* microSD */
0776 &usdhc2 {
0777 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0778 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0779 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0780 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0781 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0782 bus-width = <4>;
0783 vmmc-supply = <®_3p3v>;
0784 status = "okay";
0785 };
0786
0787 /* eMMC */
0788 &usdhc3 {
0789 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0790 pinctrl-0 = <&pinctrl_usdhc3>;
0791 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0792 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0793 bus-width = <8>;
0794 non-removable;
0795 status = "okay";
0796 };
0797
0798 &wdog1 {
0799 pinctrl-names = "default";
0800 pinctrl-0 = <&pinctrl_wdog>;
0801 fsl,ext-reset-output;
0802 status = "okay";
0803 };
0804
0805 &iomuxc {
0806 pinctrl-names = "default";
0807 pinctrl-0 = <&pinctrl_hog>;
0808
0809 pinctrl_hog: hoggrp {
0810 fsl,pins = <
0811 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
0812 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
0813 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
0814 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
0815 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
0816 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
0817 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
0818 >;
0819 };
0820
0821 pinctrl_fec1: fec1grp {
0822 fsl,pins = <
0823 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0824 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0825 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0826 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0827 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0828 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0829 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0830 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0831 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0832 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0833 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0834 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0835 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0836 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0837 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
0838 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
0839 >;
0840 };
0841
0842 pinctrl_gsc: gscgrp {
0843 fsl,pins = <
0844 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
0845 >;
0846 };
0847
0848 pinctrl_i2c1: i2c1grp {
0849 fsl,pins = <
0850 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0851 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0852 >;
0853 };
0854
0855 pinctrl_i2c2: i2c2grp {
0856 fsl,pins = <
0857 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0858 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0859 >;
0860 };
0861
0862 pinctrl_i2c3: i2c3grp {
0863 fsl,pins = <
0864 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0865 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0866 >;
0867 };
0868
0869 pinctrl_i2c4: i2c4grp {
0870 fsl,pins = <
0871 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
0872 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
0873 >;
0874 };
0875
0876 pinctrl_ksz: kszgrp {
0877 fsl,pins = <
0878 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
0879 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
0880 >;
0881 };
0882
0883 pinctrl_pcie0: pciegrp {
0884 fsl,pins = <
0885 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
0886 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
0887 >;
0888 };
0889
0890 pinctrl_pmic: pmicgrp {
0891 fsl,pins = <
0892 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
0893 >;
0894 };
0895
0896 pinctrl_reg_isouart: regisouartgrp {
0897 fsl,pins = <
0898 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
0899 >;
0900 };
0901
0902 pinctrl_reg_ioexp: regioexpgrp {
0903 fsl,pins = <
0904 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
0905 >;
0906 };
0907
0908 pinctrl_reg_wl: regwlgrp {
0909 fsl,pins = <
0910 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
0911 >;
0912 };
0913
0914 pinctrl_reg_usb2: regusb1grp {
0915 fsl,pins = <
0916 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41
0917 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140
0918 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140
0919 >;
0920 };
0921
0922 pinctrl_spi1: spi1grp {
0923 fsl,pins = <
0924 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
0925 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
0926 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
0927 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
0928 >;
0929 };
0930
0931 pinctrl_uart1: uart1grp {
0932 fsl,pins = <
0933 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0934 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0935 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
0936 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
0937 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
0938 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
0939 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
0940 >;
0941 };
0942
0943 pinctrl_uart1_gpio: uart1gpiogrp {
0944 fsl,pins = <
0945 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
0946 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
0947 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
0948 >;
0949 };
0950
0951 pinctrl_uart2: uart2grp {
0952 fsl,pins = <
0953 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0954 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0955 >;
0956 };
0957
0958 pinctrl_uart3: uart3grp {
0959 fsl,pins = <
0960 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0961 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0962 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
0963 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
0964 >;
0965 };
0966
0967 pinctrl_uart3_gpio: uart3gpiogrp {
0968 fsl,pins = <
0969 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
0970 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
0971 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
0972 >;
0973 };
0974
0975 pinctrl_uart4: uart4grp {
0976 fsl,pins = <
0977 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0978 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0979 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
0980 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
0981 >;
0982 };
0983
0984 pinctrl_uart4_gpio: uart4gpiogrp {
0985 fsl,pins = <
0986
0987 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
0988 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
0989 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
0990 >;
0991 };
0992
0993 pinctrl_usdhc1: usdhc1grp {
0994 fsl,pins = <
0995 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0996 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0997 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0998 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0999 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
1000 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
1001 >;
1002 };
1003
1004 pinctrl_usdhc2: usdhc2grp {
1005 fsl,pins = <
1006 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
1007 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
1008 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
1009 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
1010 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
1011 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
1012 >;
1013 };
1014
1015 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1016 fsl,pins = <
1017 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
1018 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
1019 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
1020 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
1021 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
1022 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
1023 >;
1024 };
1025
1026 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1027 fsl,pins = <
1028 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
1029 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
1030 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
1031 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
1032 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
1033 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
1034 >;
1035 };
1036
1037 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
1038 fsl,pins = <
1039 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
1040 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
1041 >;
1042 };
1043
1044 pinctrl_usdhc3: usdhc3grp {
1045 fsl,pins = <
1046 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
1047 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
1048 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
1049 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
1050 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
1051 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
1052 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
1053 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
1054 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
1055 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
1056 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
1057 >;
1058 };
1059
1060 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1061 fsl,pins = <
1062 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
1063 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
1064 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
1065 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
1066 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
1067 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
1068 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
1069 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
1070 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
1071 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
1072 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
1073 >;
1074 };
1075
1076 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1077 fsl,pins = <
1078 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
1079 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
1080 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
1081 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
1082 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
1083 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
1084 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
1085 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1086 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1087 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1088 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1089 >;
1090 };
1091
1092 pinctrl_wdog: wdoggrp {
1093 fsl,pins = <
1094 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1095 >;
1096 };
1097 };
