0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2020 Gateworks Corporation
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/leds/common.h>
0008 #include <dt-bindings/phy/phy-imx8-pcie.h>
0009
0010 / {
0011 aliases {
0012 ethernet1 = ð1;
0013 usb0 = &usbotg1;
0014 usb1 = &usbotg2;
0015 };
0016
0017 led-controller {
0018 compatible = "gpio-leds";
0019 pinctrl-names = "default";
0020 pinctrl-0 = <&pinctrl_gpio_leds>;
0021
0022 led-0 {
0023 function = LED_FUNCTION_STATUS;
0024 color = <LED_COLOR_ID_GREEN>;
0025 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
0026 default-state = "on";
0027 linux,default-trigger = "heartbeat";
0028 };
0029
0030 led-1 {
0031 function = LED_FUNCTION_STATUS;
0032 color = <LED_COLOR_ID_RED>;
0033 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
0034 default-state = "off";
0035 };
0036 };
0037
0038 pcie0_refclk: pcie0-refclk {
0039 compatible = "fixed-clock";
0040 #clock-cells = <0>;
0041 clock-frequency = <100000000>;
0042 };
0043
0044 pps {
0045 compatible = "pps-gpio";
0046 pinctrl-names = "default";
0047 pinctrl-0 = <&pinctrl_pps>;
0048 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
0049 status = "okay";
0050 };
0051
0052 reg_1p8v: regulator-1p8v {
0053 compatible = "regulator-fixed";
0054 regulator-name = "1P8V";
0055 regulator-min-microvolt = <1800000>;
0056 regulator-max-microvolt = <1800000>;
0057 regulator-always-on;
0058 };
0059
0060 reg_3p3v: regulator-3p3v {
0061 compatible = "regulator-fixed";
0062 regulator-name = "3P3V";
0063 regulator-min-microvolt = <3300000>;
0064 regulator-max-microvolt = <3300000>;
0065 regulator-always-on;
0066 };
0067
0068 reg_usb_otg1_vbus: regulator-usb-otg1 {
0069 pinctrl-names = "default";
0070 pinctrl-0 = <&pinctrl_reg_usb1_en>;
0071 compatible = "regulator-fixed";
0072 regulator-name = "usb_otg1_vbus";
0073 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0074 enable-active-high;
0075 regulator-min-microvolt = <5000000>;
0076 regulator-max-microvolt = <5000000>;
0077 };
0078
0079 reg_usb_otg2_vbus: regulator-usb-otg2 {
0080 pinctrl-names = "default";
0081 pinctrl-0 = <&pinctrl_reg_usb2_en>;
0082 compatible = "regulator-fixed";
0083 regulator-name = "usb_otg2_vbus";
0084 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
0085 enable-active-high;
0086 regulator-min-microvolt = <5000000>;
0087 regulator-max-microvolt = <5000000>;
0088 };
0089
0090 reg_wifi_en: regulator-wifi-en {
0091 pinctrl-names = "default";
0092 pinctrl-0 = <&pinctrl_reg_wl>;
0093 compatible = "regulator-fixed";
0094 regulator-name = "wl";
0095 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
0096 startup-delay-us = <100>;
0097 enable-active-high;
0098 regulator-min-microvolt = <3300000>;
0099 regulator-max-microvolt = <3300000>;
0100 };
0101 };
0102
0103 /* off-board header */
0104 &ecspi2 {
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&pinctrl_spi2>;
0107 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0108 status = "okay";
0109 };
0110
0111 &gpio1 {
0112 gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
0113 "", "", "pci_usb_sel", "dio0",
0114 "", "dio1", "", "", "", "", "", "",
0115 "", "", "", "", "", "", "", "",
0116 "", "", "", "", "", "", "", "";
0117 };
0118
0119 &gpio4 {
0120 gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
0121 "mipi_gpio1", "", "", "pci_wdis#",
0122 "", "", "", "", "", "", "", "",
0123 "", "", "", "", "", "", "", "",
0124 "", "", "", "", "", "", "", "";
0125 };
0126
0127 &i2c2 {
0128 clock-frequency = <400000>;
0129 pinctrl-names = "default";
0130 pinctrl-0 = <&pinctrl_i2c2>;
0131 status = "okay";
0132
0133 accelerometer@19 {
0134 pinctrl-names = "default";
0135 pinctrl-0 = <&pinctrl_accel>;
0136 compatible = "st,lis2de12";
0137 reg = <0x19>;
0138 st,drdy-int-pin = <1>;
0139 interrupt-parent = <&gpio4>;
0140 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
0141 interrupt-names = "INT1";
0142 };
0143 };
0144
0145 /* off-board header */
0146 &i2c3 {
0147 clock-frequency = <400000>;
0148 pinctrl-names = "default";
0149 pinctrl-0 = <&pinctrl_i2c3>;
0150 status = "okay";
0151 };
0152
0153 &pcie_phy {
0154 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0155 fsl,clkreq-unsupported;
0156 clocks = <&pcie0_refclk>;
0157 clock-names = "ref";
0158 status = "okay";
0159 };
0160
0161 &pcie0 {
0162 pinctrl-names = "default";
0163 pinctrl-0 = <&pinctrl_pcie0>;
0164 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
0165 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0166 <&pcie0_refclk>;
0167 clock-names = "pcie", "pcie_aux", "pcie_bus";
0168 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0169 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0170 assigned-clock-rates = <10000000>, <250000000>;
0171 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0172 <&clk IMX8MM_SYS_PLL2_250M>;
0173 status = "okay";
0174
0175 pcie@0,0 {
0176 reg = <0x0000 0 0 0 0>;
0177 #address-cells = <1>;
0178 #size-cells = <0>;
0179
0180 pcie@1,0 {
0181 reg = <0x0000 0 0 0 0>;
0182 #address-cells = <1>;
0183 #size-cells = <0>;
0184
0185 pcie@2,4 {
0186 reg = <0x2000 0 0 0 0>;
0187 #address-cells = <1>;
0188 #size-cells = <0>;
0189
0190 eth1: pcie@6,0 {
0191 reg = <0x0000 0 0 0 0>;
0192 #address-cells = <1>;
0193 #size-cells = <0>;
0194
0195 local-mac-address = [00 00 00 00 00 00];
0196 };
0197 };
0198 };
0199 };
0200 };
0201
0202 /* off-board header */
0203 &sai3 {
0204 pinctrl-names = "default";
0205 pinctrl-0 = <&pinctrl_sai3>;
0206 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
0207 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
0208 assigned-clock-rates = <24576000>;
0209 status = "okay";
0210 };
0211
0212 /* GPS */
0213 &uart1 {
0214 pinctrl-names = "default";
0215 pinctrl-0 = <&pinctrl_uart1>;
0216 status = "okay";
0217 };
0218
0219 /* bluetooth HCI */
0220 &uart3 {
0221 pinctrl-names = "default";
0222 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
0223 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
0224 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0225 uart-has-rtscts;
0226 status = "okay";
0227
0228 bluetooth {
0229 compatible = "brcm,bcm4330-bt";
0230 shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
0231 };
0232 };
0233
0234 /* RS232 */
0235 &uart4 {
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_uart4>;
0238 status = "okay";
0239 };
0240
0241 &usbotg1 {
0242 dr_mode = "otg";
0243 over-current-active-low;
0244 vbus-supply = <®_usb_otg1_vbus>;
0245 status = "okay";
0246 };
0247
0248 &usbotg2 {
0249 dr_mode = "host";
0250 disable-over-current;
0251 vbus-supply = <®_usb_otg2_vbus>;
0252 status = "okay";
0253 };
0254
0255 /* SDIO WiFi */
0256 &usdhc1 {
0257 pinctrl-names = "default";
0258 pinctrl-0 = <&pinctrl_usdhc1>;
0259 bus-width = <4>;
0260 non-removable;
0261 vmmc-supply = <®_wifi_en>;
0262 status = "okay";
0263 };
0264
0265 /* microSD */
0266 &usdhc2 {
0267 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0268 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0269 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0270 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0271 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0272 bus-width = <4>;
0273 vmmc-supply = <®_3p3v>;
0274 status = "okay";
0275 };
0276
0277 &iomuxc {
0278 pinctrl-names = "default";
0279 pinctrl-0 = <&pinctrl_hog>;
0280
0281 pinctrl_hog: hoggrp {
0282 fsl,pins = <
0283 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
0284 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
0285 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
0286 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
0287 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
0288 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
0289 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
0290 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
0291 >;
0292 };
0293
0294 pinctrl_accel: accelgrp {
0295 fsl,pins = <
0296 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
0297 >;
0298 };
0299
0300 pinctrl_bten: btengrp {
0301 fsl,pins = <
0302 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
0303 >;
0304 };
0305
0306 pinctrl_gpio_leds: gpioledgrp {
0307 fsl,pins = <
0308 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
0309 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
0310 >;
0311 };
0312
0313 pinctrl_i2c3: i2c3grp {
0314 fsl,pins = <
0315 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0316 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0317 >;
0318 };
0319
0320 pinctrl_pcie0: pcie0grp {
0321 fsl,pins = <
0322 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
0323 >;
0324 };
0325
0326 pinctrl_pps: ppsgrp {
0327 fsl,pins = <
0328 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
0329 >;
0330 };
0331
0332 pinctrl_reg_wl: regwlgrp {
0333 fsl,pins = <
0334 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
0335 >;
0336 };
0337
0338 pinctrl_reg_usb1_en: regusb1grp {
0339 fsl,pins = <
0340 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
0341 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
0342 >;
0343 };
0344
0345 pinctrl_reg_usb2_en: regusb2grp {
0346 fsl,pins = <
0347 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
0348 >;
0349 };
0350
0351 pinctrl_sai3: sai3grp {
0352 fsl,pins = <
0353 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
0354 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
0355 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
0356 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
0357 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
0358 >;
0359 };
0360
0361 pinctrl_spi2: spi2grp {
0362 fsl,pins = <
0363 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
0364 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
0365 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
0366 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
0367 >;
0368 };
0369
0370 pinctrl_uart1: uart1grp {
0371 fsl,pins = <
0372 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0373 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0374 >;
0375 };
0376
0377 pinctrl_uart3: uart3grp {
0378 fsl,pins = <
0379 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0380 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0381 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
0382 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
0383 >;
0384 };
0385
0386 pinctrl_uart4: uart4grp {
0387 fsl,pins = <
0388 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0389 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0390 >;
0391 };
0392
0393 pinctrl_usdhc1: usdhc1grp {
0394 fsl,pins = <
0395 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0396 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0397 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0398 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0399 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
0400 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
0401 >;
0402 };
0403
0404 pinctrl_usdhc2: usdhc2grp {
0405 fsl,pins = <
0406 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0407 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0408 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0409 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0410 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0411 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0412 >;
0413 };
0414
0415 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0416 fsl,pins = <
0417 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0418 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0419 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0420 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0421 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0422 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0423 >;
0424 };
0425
0426 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0427 fsl,pins = <
0428 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0429 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0430 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0431 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0432 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0433 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0434 >;
0435 };
0436
0437 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0438 fsl,pins = <
0439 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
0440 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
0441 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0442 >;
0443 };
0444 };
