0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2020 Gateworks Corporation
0004 */
0005
0006 #include <dt-bindings/gpio/gpio.h>
0007 #include <dt-bindings/input/linux-event-codes.h>
0008 #include <dt-bindings/net/ti-dp83867.h>
0009
0010 / {
0011 memory@40000000 {
0012 device_type = "memory";
0013 reg = <0x0 0x40000000 0 0x80000000>;
0014 };
0015
0016 gpio-keys {
0017 compatible = "gpio-keys";
0018
0019 key-user-pb {
0020 label = "user_pb";
0021 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
0022 linux,code = <BTN_0>;
0023 };
0024
0025 key-user-pb1x {
0026 label = "user_pb1x";
0027 linux,code = <BTN_1>;
0028 interrupt-parent = <&gsc>;
0029 interrupts = <0>;
0030 };
0031
0032 key-erased {
0033 label = "key_erased";
0034 linux,code = <BTN_2>;
0035 interrupt-parent = <&gsc>;
0036 interrupts = <1>;
0037 };
0038
0039 key-eeprom-wp {
0040 label = "eeprom_wp";
0041 linux,code = <BTN_3>;
0042 interrupt-parent = <&gsc>;
0043 interrupts = <2>;
0044 };
0045
0046 key-tamper {
0047 label = "tamper";
0048 linux,code = <BTN_4>;
0049 interrupt-parent = <&gsc>;
0050 interrupts = <5>;
0051 };
0052
0053 switch-hold {
0054 label = "switch_hold";
0055 linux,code = <BTN_5>;
0056 interrupt-parent = <&gsc>;
0057 interrupts = <7>;
0058 };
0059 };
0060 };
0061
0062 &A53_0 {
0063 cpu-supply = <&buck3_reg>;
0064 };
0065
0066 &A53_1 {
0067 cpu-supply = <&buck3_reg>;
0068 };
0069
0070 &A53_2 {
0071 cpu-supply = <&buck3_reg>;
0072 };
0073
0074 &A53_3 {
0075 cpu-supply = <&buck3_reg>;
0076 };
0077
0078 &ddrc {
0079 operating-points-v2 = <&ddrc_opp_table>;
0080
0081 ddrc_opp_table: opp-table {
0082 compatible = "operating-points-v2";
0083
0084 opp-25M {
0085 opp-hz = /bits/ 64 <25000000>;
0086 };
0087
0088 opp-100M {
0089 opp-hz = /bits/ 64 <100000000>;
0090 };
0091
0092 opp-750M {
0093 opp-hz = /bits/ 64 <750000000>;
0094 };
0095 };
0096 };
0097
0098 &fec1 {
0099 pinctrl-names = "default";
0100 pinctrl-0 = <&pinctrl_fec1>;
0101 phy-mode = "rgmii-id";
0102 phy-handle = <ðphy0>;
0103 status = "okay";
0104
0105 mdio {
0106 #address-cells = <1>;
0107 #size-cells = <0>;
0108
0109 ethphy0: ethernet-phy@0 {
0110 compatible = "ethernet-phy-ieee802.3-c22";
0111 reg = <0>;
0112 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0113 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0114 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0115 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0116 };
0117 };
0118 };
0119
0120 &i2c1 {
0121 clock-frequency = <100000>;
0122 pinctrl-names = "default";
0123 pinctrl-0 = <&pinctrl_i2c1>;
0124 status = "okay";
0125
0126 gsc: gsc@20 {
0127 compatible = "gw,gsc";
0128 reg = <0x20>;
0129 pinctrl-0 = <&pinctrl_gsc>;
0130 interrupt-parent = <&gpio2>;
0131 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
0132 interrupt-controller;
0133 #interrupt-cells = <1>;
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136
0137 adc {
0138 compatible = "gw,gsc-adc";
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141
0142 channel@6 {
0143 gw,mode = <0>;
0144 reg = <0x06>;
0145 label = "temp";
0146 };
0147
0148 channel@8 {
0149 gw,mode = <1>;
0150 reg = <0x08>;
0151 label = "vdd_bat";
0152 };
0153
0154 channel@16 {
0155 gw,mode = <4>;
0156 reg = <0x16>;
0157 label = "fan_tach";
0158 };
0159
0160 channel@82 {
0161 gw,mode = <2>;
0162 reg = <0x82>;
0163 label = "vdd_vin";
0164 gw,voltage-divider-ohms = <22100 1000>;
0165 };
0166
0167 channel@84 {
0168 gw,mode = <2>;
0169 reg = <0x84>;
0170 label = "vdd_adc1";
0171 gw,voltage-divider-ohms = <10000 10000>;
0172 };
0173
0174 channel@86 {
0175 gw,mode = <2>;
0176 reg = <0x86>;
0177 label = "vdd_adc2";
0178 gw,voltage-divider-ohms = <10000 10000>;
0179 };
0180
0181 channel@88 {
0182 gw,mode = <2>;
0183 reg = <0x88>;
0184 label = "vdd_dram";
0185 };
0186
0187 channel@8c {
0188 gw,mode = <2>;
0189 reg = <0x8c>;
0190 label = "vdd_1p2";
0191 };
0192
0193 channel@8e {
0194 gw,mode = <2>;
0195 reg = <0x8e>;
0196 label = "vdd_1p0";
0197 };
0198
0199 channel@90 {
0200 gw,mode = <2>;
0201 reg = <0x90>;
0202 label = "vdd_2p5";
0203 gw,voltage-divider-ohms = <10000 10000>;
0204 };
0205
0206 channel@92 {
0207 gw,mode = <2>;
0208 reg = <0x92>;
0209 label = "vdd_3p3";
0210 gw,voltage-divider-ohms = <10000 10000>;
0211 };
0212
0213 channel@98 {
0214 gw,mode = <2>;
0215 reg = <0x98>;
0216 label = "vdd_0p95";
0217 };
0218
0219 channel@9a {
0220 gw,mode = <2>;
0221 reg = <0x9a>;
0222 label = "vdd_1p8";
0223 };
0224
0225 channel@a2 {
0226 gw,mode = <2>;
0227 reg = <0xa2>;
0228 label = "vdd_gsc";
0229 gw,voltage-divider-ohms = <10000 10000>;
0230 };
0231 };
0232
0233 fan-controller@0 {
0234 #address-cells = <1>;
0235 #size-cells = <0>;
0236 compatible = "gw,gsc-fan";
0237 reg = <0x0a>;
0238 };
0239 };
0240
0241 gpio: gpio@23 {
0242 compatible = "nxp,pca9555";
0243 reg = <0x23>;
0244 gpio-controller;
0245 #gpio-cells = <2>;
0246 interrupt-parent = <&gsc>;
0247 interrupts = <4>;
0248 };
0249
0250 eeprom@50 {
0251 compatible = "atmel,24c02";
0252 reg = <0x50>;
0253 pagesize = <16>;
0254 };
0255
0256 eeprom@51 {
0257 compatible = "atmel,24c02";
0258 reg = <0x51>;
0259 pagesize = <16>;
0260 };
0261
0262 eeprom@52 {
0263 compatible = "atmel,24c02";
0264 reg = <0x52>;
0265 pagesize = <16>;
0266 };
0267
0268 eeprom@53 {
0269 compatible = "atmel,24c02";
0270 reg = <0x53>;
0271 pagesize = <16>;
0272 };
0273
0274 rtc@68 {
0275 compatible = "dallas,ds1672";
0276 reg = <0x68>;
0277 };
0278
0279 pmic@69 {
0280 compatible = "mps,mp5416";
0281 reg = <0x69>;
0282
0283 regulators {
0284 /* vdd_0p95: DRAM/GPU/VPU */
0285 buck1 {
0286 regulator-name = "buck1";
0287 regulator-min-microvolt = <800000>;
0288 regulator-max-microvolt = <1000000>;
0289 regulator-min-microamp = <3800000>;
0290 regulator-max-microamp = <6800000>;
0291 regulator-boot-on;
0292 regulator-always-on;
0293 };
0294
0295 /* vdd_soc */
0296 buck2 {
0297 regulator-name = "buck2";
0298 regulator-min-microvolt = <800000>;
0299 regulator-max-microvolt = <900000>;
0300 regulator-min-microamp = <2200000>;
0301 regulator-max-microamp = <5200000>;
0302 regulator-boot-on;
0303 regulator-always-on;
0304 };
0305
0306 /* vdd_arm */
0307 buck3_reg: buck3 {
0308 regulator-name = "buck3";
0309 regulator-min-microvolt = <800000>;
0310 regulator-max-microvolt = <1000000>;
0311 regulator-min-microamp = <3800000>;
0312 regulator-max-microamp = <6800000>;
0313 regulator-always-on;
0314 };
0315
0316 /* vdd_1p8 */
0317 buck4 {
0318 regulator-name = "buck4";
0319 regulator-min-microvolt = <1800000>;
0320 regulator-max-microvolt = <1800000>;
0321 regulator-min-microamp = <2200000>;
0322 regulator-max-microamp = <5200000>;
0323 regulator-boot-on;
0324 regulator-always-on;
0325 };
0326
0327 /* nvcc_snvs_1p8 */
0328 ldo1 {
0329 regulator-name = "ldo1";
0330 regulator-min-microvolt = <1800000>;
0331 regulator-max-microvolt = <1800000>;
0332 regulator-boot-on;
0333 regulator-always-on;
0334 };
0335
0336 /* vdd_snvs_0p8 */
0337 ldo2 {
0338 regulator-name = "ldo2";
0339 regulator-min-microvolt = <800000>;
0340 regulator-max-microvolt = <800000>;
0341 regulator-boot-on;
0342 regulator-always-on;
0343 };
0344
0345 /* vdd_0p9 */
0346 ldo3 {
0347 regulator-name = "ldo3";
0348 regulator-min-microvolt = <900000>;
0349 regulator-max-microvolt = <900000>;
0350 regulator-boot-on;
0351 regulator-always-on;
0352 };
0353
0354 /* vdd_1p8 */
0355 ldo4 {
0356 regulator-name = "ldo4";
0357 regulator-min-microvolt = <1800000>;
0358 regulator-max-microvolt = <1800000>;
0359 regulator-boot-on;
0360 regulator-always-on;
0361 };
0362 };
0363 };
0364 };
0365
0366 &i2c2 {
0367 clock-frequency = <400000>;
0368 pinctrl-names = "default";
0369 pinctrl-0 = <&pinctrl_i2c2>;
0370 status = "okay";
0371
0372 eeprom@52 {
0373 compatible = "atmel,24c32";
0374 reg = <0x52>;
0375 pagesize = <32>;
0376 };
0377 };
0378
0379 /* console */
0380 &uart2 {
0381 pinctrl-names = "default";
0382 pinctrl-0 = <&pinctrl_uart2>;
0383 status = "okay";
0384 };
0385
0386 /* eMMC */
0387 &usdhc3 {
0388 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0389 pinctrl-0 = <&pinctrl_usdhc3>;
0390 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0391 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0392 bus-width = <8>;
0393 non-removable;
0394 status = "okay";
0395 };
0396
0397 &wdog1 {
0398 pinctrl-names = "default";
0399 pinctrl-0 = <&pinctrl_wdog>;
0400 fsl,ext-reset-output;
0401 status = "okay";
0402 };
0403
0404 &iomuxc {
0405 pinctrl_fec1: fec1grp {
0406 fsl,pins = <
0407 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0408 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0409 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0410 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0411 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0412 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0413 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0414 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0415 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0416 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0417 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0418 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0419 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0420 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0421 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
0422 >;
0423 };
0424
0425 pinctrl_gsc: gscgrp {
0426 fsl,pins = <
0427 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
0428 >;
0429 };
0430
0431 pinctrl_i2c1: i2c1grp {
0432 fsl,pins = <
0433 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0434 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0435 >;
0436 };
0437
0438 pinctrl_i2c2: i2c2grp {
0439 fsl,pins = <
0440 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0441 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0442 >;
0443 };
0444
0445 pinctrl_uart2: uart2grp {
0446 fsl,pins = <
0447 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0448 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0449 >;
0450 };
0451
0452 pinctrl_usdhc3: usdhc3grp {
0453 fsl,pins = <
0454 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0455 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0456 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0457 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0458 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0459 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0460 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0461 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0462 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0463 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0464 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0465 >;
0466 };
0467
0468 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0469 fsl,pins = <
0470 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0471 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0472 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0473 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0474 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0475 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0476 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0477 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0478 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0479 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0480 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0481 >;
0482 };
0483
0484 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0485 fsl,pins = <
0486 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0487 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0488 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0489 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0490 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0491 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0492 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0493 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0494 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0495 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0496 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0497 >;
0498 };
0499
0500 pinctrl_wdog: wdoggrp {
0501 fsl,pins = <
0502 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0503 >;
0504 };
0505 };
