0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx8mm-var-som.dtsi"
0009
0010 / {
0011 model = "Variscite VAR-SOM-MX8MM Symphony evaluation board";
0012 compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm";
0013
0014 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
0015 compatible = "regulator-fixed";
0016 pinctrl-names = "default";
0017 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
0018 regulator-name = "VSD_3V3";
0019 regulator-min-microvolt = <3300000>;
0020 regulator-max-microvolt = <3300000>;
0021 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0022 enable-active-high;
0023 };
0024
0025 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
0026 compatible = "regulator-fixed";
0027 pinctrl-names = "default";
0028 pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
0029 regulator-name = "usb_otg2_vbus";
0030 regulator-min-microvolt = <5000000>;
0031 regulator-max-microvolt = <5000000>;
0032 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
0033 enable-active-high;
0034 };
0035
0036 gpio-keys {
0037 compatible = "gpio-keys";
0038
0039 key-back {
0040 label = "Back";
0041 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
0042 linux,code = <KEY_BACK>;
0043 };
0044
0045 key-home {
0046 label = "Home";
0047 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
0048 linux,code = <KEY_HOME>;
0049 };
0050
0051 key-menu {
0052 label = "Menu";
0053 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
0054 linux,code = <KEY_MENU>;
0055 };
0056 };
0057
0058 leds {
0059 compatible = "gpio-leds";
0060
0061 led {
0062 label = "Heartbeat";
0063 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
0064 linux,default-trigger = "heartbeat";
0065 };
0066 };
0067 };
0068
0069 ðphy {
0070 reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
0071 };
0072
0073 &i2c2 {
0074 clock-frequency = <400000>;
0075 pinctrl-names = "default";
0076 pinctrl-0 = <&pinctrl_i2c2>;
0077 status = "okay";
0078
0079 pca9534: gpio@20 {
0080 compatible = "nxp,pca9534";
0081 reg = <0x20>;
0082 gpio-controller;
0083 pinctrl-names = "default";
0084 pinctrl-0 = <&pinctrl_pca9534>;
0085 interrupt-parent = <&gpio1>;
0086 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
0087 #gpio-cells = <2>;
0088 wakeup-source;
0089
0090 /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
0091 usb3-sata-sel-hog {
0092 gpio-hog;
0093 gpios = <4 GPIO_ACTIVE_HIGH>;
0094 output-low;
0095 line-name = "usb3_sata_sel";
0096 };
0097
0098 som-vselect-hog {
0099 gpio-hog;
0100 gpios = <6 GPIO_ACTIVE_HIGH>;
0101 output-low;
0102 line-name = "som_vselect";
0103 };
0104
0105 enet-sel-hog {
0106 gpio-hog;
0107 gpios = <7 GPIO_ACTIVE_HIGH>;
0108 output-low;
0109 line-name = "enet_sel";
0110 };
0111 };
0112
0113 extcon_usbotg1: typec@3d {
0114 compatible = "nxp,ptn5150";
0115 reg = <0x3d>;
0116 interrupt-parent = <&gpio1>;
0117 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
0118 pinctrl-names = "default";
0119 pinctrl-0 = <&pinctrl_ptn5150>;
0120 status = "okay";
0121 };
0122 };
0123
0124 &i2c3 {
0125 /* Capacitive touch controller */
0126 ft5x06_ts: touchscreen@38 {
0127 compatible = "edt,edt-ft5406";
0128 reg = <0x38>;
0129 pinctrl-names = "default";
0130 pinctrl-0 = <&pinctrl_captouch>;
0131 interrupt-parent = <&gpio5>;
0132 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0133
0134 touchscreen-size-x = <800>;
0135 touchscreen-size-y = <480>;
0136 touchscreen-inverted-x;
0137 touchscreen-inverted-y;
0138 };
0139
0140 rtc@68 {
0141 compatible = "dallas,ds1337";
0142 reg = <0x68>;
0143 };
0144 };
0145
0146 /* Header */
0147 &uart1 {
0148 pinctrl-names = "default";
0149 pinctrl-0 = <&pinctrl_uart1>;
0150 status = "okay";
0151 };
0152
0153 /* Header */
0154 &uart3 {
0155 pinctrl-names = "default";
0156 pinctrl-0 = <&pinctrl_uart3>;
0157 status = "okay";
0158 };
0159
0160 &usbotg1 {
0161 disable-over-current;
0162 extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
0163 };
0164
0165 &usbotg2 {
0166 dr_mode = "host";
0167 vbus-supply = <®_usb_otg2_vbus>;
0168 srp-disable;
0169 hnp-disable;
0170 adp-disable;
0171 disable-over-current;
0172 /delete-property/ usb-role-switch;
0173 /*
0174 * FIXME: having USB2 enabled hangs the boot just after:
0175 * [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller
0176 * [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1
0177 * [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
0178 * [ 1.977203] hub 1-0:1.0: USB hub found
0179 * [ 1.980987] hub 1-0:1.0: 1 port detected
0180 */
0181 status = "disabled";
0182 };
0183
0184 &pinctrl_fec1 {
0185 fsl,pins = <
0186 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0187 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0188 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0189 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0190 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0191 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0192 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0193 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0194 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0195 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0196 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0197 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0198 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0199 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0200 /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
0201 >;
0202 };
0203
0204 &iomuxc {
0205 pinctrl_captouch: captouchgrp {
0206 fsl,pins = <
0207 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
0208 >;
0209 };
0210
0211 pinctrl_i2c2: i2c2grp {
0212 fsl,pins = <
0213 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0214 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0215 >;
0216 };
0217
0218 pinctrl_pca9534: pca9534grp {
0219 fsl,pins = <
0220 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
0221 >;
0222 };
0223
0224 pinctrl_ptn5150: ptn5150grp {
0225 fsl,pins = <
0226 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
0227 >;
0228 };
0229
0230 pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp {
0231 fsl,pins = <
0232 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16
0233 >;
0234 };
0235
0236 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0237 fsl,pins = <
0238 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
0239 >;
0240 };
0241
0242 pinctrl_uart1: uart1grp {
0243 fsl,pins = <
0244 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0245 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0246 >;
0247 };
0248
0249 pinctrl_uart3: uart3grp {
0250 fsl,pins = <
0251 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0252 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0253 >;
0254 };
0255 };
