0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2021 NXP
0004 * Dong Aisheng <aisheng.dong@nxp.com>
0005 */
0006
0007 vpu: vpu@2c000000 {
0008 #address-cells = <1>;
0009 #size-cells = <1>;
0010 ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
0011 reg = <0 0x2c000000 0 0x1000000>;
0012 power-domains = <&pd IMX_SC_R_VPU>;
0013 status = "disabled";
0014
0015 mu_m0: mailbox@2d000000 {
0016 compatible = "fsl,imx6sx-mu";
0017 reg = <0x2d000000 0x20000>;
0018 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
0019 #mbox-cells = <2>;
0020 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
0021 status = "disabled";
0022 };
0023
0024 mu1_m0: mailbox@2d020000 {
0025 compatible = "fsl,imx6sx-mu";
0026 reg = <0x2d020000 0x20000>;
0027 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
0028 #mbox-cells = <2>;
0029 power-domains = <&pd IMX_SC_R_VPU_MU_1>;
0030 status = "disabled";
0031 };
0032
0033 mu2_m0: mailbox@2d040000 {
0034 compatible = "fsl,imx6sx-mu";
0035 reg = <0x2d040000 0x20000>;
0036 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
0037 #mbox-cells = <2>;
0038 power-domains = <&pd IMX_SC_R_VPU_MU_2>;
0039 status = "disabled";
0040 };
0041
0042 vpu_core0: vpu-core@2d080000 {
0043 reg = <0x2d080000 0x10000>;
0044 compatible = "nxp,imx8q-vpu-decoder";
0045 power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
0046 mbox-names = "tx0", "tx1", "rx";
0047 mboxes = <&mu_m0 0 0>,
0048 <&mu_m0 0 1>,
0049 <&mu_m0 1 0>;
0050 status = "disabled";
0051 };
0052
0053 vpu_core1: vpu-core@2d090000 {
0054 reg = <0x2d090000 0x10000>;
0055 compatible = "nxp,imx8q-vpu-encoder";
0056 power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
0057 mbox-names = "tx0", "tx1", "rx";
0058 mboxes = <&mu1_m0 0 0>,
0059 <&mu1_m0 0 1>,
0060 <&mu1_m0 1 0>;
0061 status = "disabled";
0062 };
0063
0064 vpu_core2: vpu-core@2d0a0000 {
0065 reg = <0x2d0a0000 0x10000>;
0066 compatible = "nxp,imx8q-vpu-encoder";
0067 power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
0068 mbox-names = "tx0", "tx1", "rx";
0069 mboxes = <&mu2_m0 0 0>,
0070 <&mu2_m0 0 1>,
0071 <&mu2_m0 1 0>;
0072 status = "disabled";
0073 };
0074 };
