0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2018-2019 NXP
0004 * Dong Aisheng <aisheng.dong@nxp.com>
0005 */
0006
0007 #include <dt-bindings/clock/imx8-lpcg.h>
0008 #include <dt-bindings/firmware/imx/rsrc.h>
0009
0010 audio_subsys: bus@59000000 {
0011 compatible = "simple-bus";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 ranges = <0x59000000 0x0 0x59000000 0x1000000>;
0015
0016 audio_ipg_clk: clock-audio-ipg {
0017 compatible = "fixed-clock";
0018 #clock-cells = <0>;
0019 clock-frequency = <120000000>;
0020 clock-output-names = "audio_ipg_clk";
0021 };
0022
0023 dsp_lpcg: clock-controller@59580000 {
0024 compatible = "fsl,imx8qxp-lpcg";
0025 reg = <0x59580000 0x10000>;
0026 #clock-cells = <1>;
0027 clocks = <&audio_ipg_clk>,
0028 <&audio_ipg_clk>,
0029 <&audio_ipg_clk>;
0030 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
0031 <IMX_LPCG_CLK_7>;
0032 clock-output-names = "dsp_lpcg_adb_clk",
0033 "dsp_lpcg_ipg_clk",
0034 "dsp_lpcg_core_clk";
0035 power-domains = <&pd IMX_SC_R_DSP>;
0036 };
0037
0038 dsp_ram_lpcg: clock-controller@59590000 {
0039 compatible = "fsl,imx8qxp-lpcg";
0040 reg = <0x59590000 0x10000>;
0041 #clock-cells = <1>;
0042 clocks = <&audio_ipg_clk>;
0043 clock-indices = <IMX_LPCG_CLK_4>;
0044 clock-output-names = "dsp_ram_lpcg_ipg_clk";
0045 power-domains = <&pd IMX_SC_R_DSP_RAM>;
0046 };
0047
0048 dsp: dsp@596e8000 {
0049 compatible = "fsl,imx8qxp-dsp";
0050 reg = <0x596e8000 0x88000>;
0051 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
0052 <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
0053 <&dsp_lpcg IMX_LPCG_CLK_7>;
0054 clock-names = "ipg", "ocram", "core";
0055 power-domains = <&pd IMX_SC_R_MU_13A>,
0056 <&pd IMX_SC_R_MU_13B>,
0057 <&pd IMX_SC_R_DSP>,
0058 <&pd IMX_SC_R_DSP_RAM>;
0059 mbox-names = "txdb0", "txdb1",
0060 "rxdb0", "rxdb1";
0061 mboxes = <&lsio_mu13 2 0>,
0062 <&lsio_mu13 2 1>,
0063 <&lsio_mu13 3 0>,
0064 <&lsio_mu13 3 1>;
0065 memory-region = <&dsp_reserved>;
0066 status = "disabled";
0067 };
0068 };
