0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 //
0003 // Device Tree file for LX2162AQDS
0004 //
0005 // Copyright 2020 NXP
0006
0007 /dts-v1/;
0008
0009 #include "fsl-lx2160a.dtsi"
0010
0011 / {
0012 model = "NXP Layerscape LX2162AQDS";
0013 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
0014
0015 aliases {
0016 crypto = &crypto;
0017 mmc0 = &esdhc0;
0018 mmc1 = &esdhc1;
0019 serial0 = &uart0;
0020 };
0021
0022 chosen {
0023 stdout-path = "serial0:115200n8";
0024 };
0025
0026 sb_3v3: regulator-sb3v3 {
0027 compatible = "regulator-fixed";
0028 regulator-name = "LTM4619-3.3VSB";
0029 regulator-min-microvolt = <3300000>;
0030 regulator-max-microvolt = <3300000>;
0031 };
0032
0033 mdio-mux-1 {
0034 compatible = "mdio-mux-multiplexer";
0035 mux-controls = <&mux 0>;
0036 mdio-parent-bus = <&emdio1>;
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039
0040 mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
0041 reg = <0x00>;
0042 #address-cells = <1>;
0043 #size-cells = <0>;
0044
0045 rgmii_phy1: ethernet-phy@1 {
0046 compatible = "ethernet-phy-id001c.c916";
0047 reg = <0x1>;
0048 eee-broken-1000t;
0049 };
0050 };
0051
0052 mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */
0053 reg = <0x8>;
0054 #address-cells = <1>;
0055 #size-cells = <0>;
0056
0057 rgmii_phy2: ethernet-phy@2 {
0058 compatible = "ethernet-phy-id001c.c916";
0059 reg = <0x2>;
0060 eee-broken-1000t;
0061 };
0062 };
0063
0064 mdio@18 { /* Slot #1 */
0065 reg = <0x18>;
0066 #address-cells = <1>;
0067 #size-cells = <0>;
0068 };
0069
0070 mdio@19 { /* Slot #2 */
0071 reg = <0x19>;
0072 #address-cells = <1>;
0073 #size-cells = <0>;
0074 };
0075
0076 mdio@1a { /* Slot #3 */
0077 reg = <0x1a>;
0078 #address-cells = <1>;
0079 #size-cells = <0>;
0080 };
0081
0082 mdio@1b { /* Slot #4 */
0083 reg = <0x1b>;
0084 #address-cells = <1>;
0085 #size-cells = <0>;
0086 };
0087
0088 mdio@1c { /* Slot #5 */
0089 reg = <0x1c>;
0090 #address-cells = <1>;
0091 #size-cells = <0>;
0092 };
0093
0094 mdio@1d { /* Slot #6 */
0095 reg = <0x1d>;
0096 #address-cells = <1>;
0097 #size-cells = <0>;
0098 };
0099
0100 mdio@1e { /* Slot #7 */
0101 reg = <0x1e>;
0102 #address-cells = <1>;
0103 #size-cells = <0>;
0104 };
0105
0106 mdio@1f { /* Slot #8 */
0107 reg = <0x1f>;
0108 #address-cells = <1>;
0109 #size-cells = <0>;
0110 };
0111 };
0112
0113 mdio-mux-2 {
0114 compatible = "mdio-mux-multiplexer";
0115 mux-controls = <&mux 1>;
0116 mdio-parent-bus = <&emdio2>;
0117 #address-cells = <1>;
0118 #size-cells = <0>;
0119
0120 mdio@0 { /* Slot #1 (secondary EMI) */
0121 reg = <0x00>;
0122 #address-cells = <1>;
0123 #size-cells = <0>;
0124 };
0125
0126 mdio@1 { /* Slot #2 (secondary EMI) */
0127 reg = <0x01>;
0128 #address-cells = <1>;
0129 #size-cells = <0>;
0130 };
0131
0132 mdio@2 { /* Slot #3 (secondary EMI) */
0133 reg = <0x02>;
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136 };
0137
0138 mdio@3 { /* Slot #4 (secondary EMI) */
0139 reg = <0x03>;
0140 #address-cells = <1>;
0141 #size-cells = <0>;
0142 };
0143
0144 mdio@4 { /* Slot #5 (secondary EMI) */
0145 reg = <0x04>;
0146 #address-cells = <1>;
0147 #size-cells = <0>;
0148 };
0149
0150 mdio@5 { /* Slot #6 (secondary EMI) */
0151 reg = <0x05>;
0152 #address-cells = <1>;
0153 #size-cells = <0>;
0154 };
0155
0156 mdio@6 { /* Slot #7 (secondary EMI) */
0157 reg = <0x06>;
0158 #address-cells = <1>;
0159 #size-cells = <0>;
0160 };
0161
0162 mdio@7 { /* Slot #8 (secondary EMI) */
0163 reg = <0x07>;
0164 #address-cells = <1>;
0165 #size-cells = <0>;
0166 };
0167 };
0168 };
0169
0170 &can0 {
0171 status = "okay";
0172 };
0173
0174 &can1 {
0175 status = "okay";
0176 };
0177
0178 &crypto {
0179 status = "okay";
0180 };
0181
0182 &dpmac17 {
0183 phy-handle = <&rgmii_phy1>;
0184 phy-connection-type = "rgmii-id";
0185 };
0186
0187 &dpmac18 {
0188 phy-handle = <&rgmii_phy2>;
0189 phy-connection-type = "rgmii-id";
0190 };
0191
0192 &dspi0 {
0193 status = "okay";
0194
0195 dflash0: flash@0 {
0196 #address-cells = <1>;
0197 #size-cells = <1>;
0198 compatible = "jedec,spi-nor";
0199 reg = <0>;
0200 spi-max-frequency = <1000000>;
0201 };
0202 };
0203
0204 &dspi1 {
0205 status = "okay";
0206
0207 dflash1: flash@0 {
0208 #address-cells = <1>;
0209 #size-cells = <1>;
0210 compatible = "jedec,spi-nor";
0211 reg = <0>;
0212 spi-max-frequency = <1000000>;
0213 };
0214 };
0215
0216 &dspi2 {
0217 status = "okay";
0218
0219 dflash2: flash@0 {
0220 #address-cells = <1>;
0221 #size-cells = <1>;
0222 compatible = "jedec,spi-nor";
0223 reg = <0>;
0224 spi-max-frequency = <1000000>;
0225 };
0226 };
0227
0228 &emdio1 {
0229 status = "okay";
0230 };
0231
0232 &emdio2 {
0233 status = "okay";
0234 };
0235
0236 &esdhc0 {
0237 sd-uhs-sdr104;
0238 sd-uhs-sdr50;
0239 sd-uhs-sdr25;
0240 sd-uhs-sdr12;
0241 status = "okay";
0242 };
0243
0244 &esdhc1 {
0245 mmc-hs200-1_8v;
0246 mmc-hs400-1_8v;
0247 bus-width = <8>;
0248 status = "okay";
0249 };
0250
0251 &fspi {
0252 status = "okay";
0253
0254 mt35xu512aba0: flash@0 {
0255 #address-cells = <1>;
0256 #size-cells = <1>;
0257 compatible = "jedec,spi-nor";
0258 m25p,fast-read;
0259 spi-max-frequency = <50000000>;
0260 reg = <0>;
0261 spi-rx-bus-width = <8>;
0262 spi-tx-bus-width = <8>;
0263 };
0264 };
0265
0266 &i2c0 {
0267 status = "okay";
0268
0269 fpga@66 {
0270 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
0271 "simple-mfd";
0272 reg = <0x66>;
0273
0274 mux: mux-controller {
0275 compatible = "reg-mux";
0276 #mux-control-cells = <1>;
0277 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
0278 <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
0279 };
0280 };
0281
0282 i2c-mux@77 {
0283 compatible = "nxp,pca9547";
0284 reg = <0x77>;
0285 #address-cells = <1>;
0286 #size-cells = <0>;
0287
0288 i2c@2 {
0289 #address-cells = <1>;
0290 #size-cells = <0>;
0291 reg = <0x2>;
0292
0293 power-monitor@40 {
0294 compatible = "ti,ina220";
0295 reg = <0x40>;
0296 shunt-resistor = <500>;
0297 };
0298
0299 power-monitor@41 {
0300 compatible = "ti,ina220";
0301 reg = <0x41>;
0302 shunt-resistor = <1000>;
0303 };
0304 };
0305
0306 i2c@3 {
0307 #address-cells = <1>;
0308 #size-cells = <0>;
0309 reg = <0x3>;
0310
0311 temperature-sensor@4c {
0312 compatible = "nxp,sa56004";
0313 reg = <0x4c>;
0314 vcc-supply = <&sb_3v3>;
0315 };
0316
0317 rtc@51 {
0318 compatible = "nxp,pcf2129";
0319 reg = <0x51>;
0320 /* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */
0321 interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
0322 };
0323 };
0324 };
0325 };
0326
0327 &optee {
0328 status = "okay";
0329 };
0330
0331 &sata0 {
0332 status = "okay";
0333 };
0334
0335 &sata1 {
0336 status = "okay";
0337 };
0338
0339 &sata2 {
0340 status = "okay";
0341 };
0342
0343 &sata3 {
0344 status = "okay";
0345 };
0346
0347 &uart0 {
0348 status = "okay";
0349 };
0350
0351 &uart1 {
0352 status = "okay";
0353 };
0354
0355 &usb0 {
0356 status = "okay";
0357 };
