0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree Include file for NXP Layerscape-1046A family SoC.
0004 *
0005 * Copyright 2016 Freescale Semiconductor, Inc.
0006 * Copyright 2018, 2020 NXP
0007 *
0008 * Mingkai Hu <mingkai.hu@nxp.com>
0009 */
0010
0011 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014
0015 / {
0016 compatible = "fsl,ls1046a";
0017 interrupt-parent = <&gic>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 aliases {
0022 crypto = &crypto;
0023 fman0 = &fman0;
0024 ethernet0 = &enet0;
0025 ethernet1 = &enet1;
0026 ethernet2 = &enet2;
0027 ethernet3 = &enet3;
0028 ethernet4 = &enet4;
0029 ethernet5 = &enet5;
0030 ethernet6 = &enet6;
0031 ethernet7 = &enet7;
0032 rtc1 = &ftm_alarm0;
0033 };
0034
0035 cpus {
0036 #address-cells = <1>;
0037 #size-cells = <0>;
0038
0039 cpu0: cpu@0 {
0040 device_type = "cpu";
0041 compatible = "arm,cortex-a72";
0042 reg = <0x0>;
0043 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0044 next-level-cache = <&l2>;
0045 cpu-idle-states = <&CPU_PH20>;
0046 #cooling-cells = <2>;
0047 };
0048
0049 cpu1: cpu@1 {
0050 device_type = "cpu";
0051 compatible = "arm,cortex-a72";
0052 reg = <0x1>;
0053 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0054 next-level-cache = <&l2>;
0055 cpu-idle-states = <&CPU_PH20>;
0056 #cooling-cells = <2>;
0057 };
0058
0059 cpu2: cpu@2 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a72";
0062 reg = <0x2>;
0063 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0064 next-level-cache = <&l2>;
0065 cpu-idle-states = <&CPU_PH20>;
0066 #cooling-cells = <2>;
0067 };
0068
0069 cpu3: cpu@3 {
0070 device_type = "cpu";
0071 compatible = "arm,cortex-a72";
0072 reg = <0x3>;
0073 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
0074 next-level-cache = <&l2>;
0075 cpu-idle-states = <&CPU_PH20>;
0076 #cooling-cells = <2>;
0077 };
0078
0079 l2: l2-cache {
0080 compatible = "cache";
0081 };
0082 };
0083
0084 idle-states {
0085 /*
0086 * PSCI node is not added default, U-boot will add missing
0087 * parts if it determines to use PSCI.
0088 */
0089 entry-method = "psci";
0090
0091 CPU_PH20: cpu-ph20 {
0092 compatible = "arm,idle-state";
0093 idle-state-name = "PH20";
0094 arm,psci-suspend-param = <0x0>;
0095 entry-latency-us = <1000>;
0096 exit-latency-us = <1000>;
0097 min-residency-us = <3000>;
0098 };
0099 };
0100
0101 memory@80000000 {
0102 device_type = "memory";
0103 /* Real size will be filled by bootloader */
0104 reg = <0x0 0x80000000 0x0 0x0>;
0105 };
0106
0107 sysclk: sysclk {
0108 compatible = "fixed-clock";
0109 #clock-cells = <0>;
0110 clock-frequency = <100000000>;
0111 clock-output-names = "sysclk";
0112 };
0113
0114 reboot {
0115 compatible = "syscon-reboot";
0116 regmap = <&dcfg>;
0117 offset = <0xb0>;
0118 mask = <0x02>;
0119 };
0120
0121 thermal-zones {
0122 ddr-controller {
0123 polling-delay-passive = <1000>;
0124 polling-delay = <5000>;
0125 thermal-sensors = <&tmu 0>;
0126
0127 trips {
0128 ddr-ctrler-alert {
0129 temperature = <85000>;
0130 hysteresis = <2000>;
0131 type = "passive";
0132 };
0133
0134 ddr-ctrler-crit {
0135 temperature = <95000>;
0136 hysteresis = <2000>;
0137 type = "critical";
0138 };
0139 };
0140 };
0141
0142 serdes {
0143 polling-delay-passive = <1000>;
0144 polling-delay = <5000>;
0145 thermal-sensors = <&tmu 1>;
0146
0147 trips {
0148 serdes-alert {
0149 temperature = <85000>;
0150 hysteresis = <2000>;
0151 type = "passive";
0152 };
0153
0154 serdes-crit {
0155 temperature = <95000>;
0156 hysteresis = <2000>;
0157 type = "critical";
0158 };
0159 };
0160 };
0161
0162 fman {
0163 polling-delay-passive = <1000>;
0164 polling-delay = <5000>;
0165 thermal-sensors = <&tmu 2>;
0166
0167 trips {
0168 fman-alert {
0169 temperature = <85000>;
0170 hysteresis = <2000>;
0171 type = "passive";
0172 };
0173
0174 fman-crit {
0175 temperature = <95000>;
0176 hysteresis = <2000>;
0177 type = "critical";
0178 };
0179 };
0180 };
0181
0182 core-cluster {
0183 polling-delay-passive = <1000>;
0184 polling-delay = <5000>;
0185 thermal-sensors = <&tmu 3>;
0186
0187 trips {
0188 core_cluster_alert: core-cluster-alert {
0189 temperature = <85000>;
0190 hysteresis = <2000>;
0191 type = "passive";
0192 };
0193
0194 core_cluster_crit: core-cluster-crit {
0195 temperature = <95000>;
0196 hysteresis = <2000>;
0197 type = "critical";
0198 };
0199 };
0200
0201 cooling-maps {
0202 map0 {
0203 trip = <&core_cluster_alert>;
0204 cooling-device =
0205 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0206 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0207 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0208 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0209 };
0210 };
0211 };
0212
0213 sec {
0214 polling-delay-passive = <1000>;
0215 polling-delay = <5000>;
0216 thermal-sensors = <&tmu 4>;
0217
0218 trips {
0219 sec-alert {
0220 temperature = <85000>;
0221 hysteresis = <2000>;
0222 type = "passive";
0223 };
0224
0225 sec-crit {
0226 temperature = <95000>;
0227 hysteresis = <2000>;
0228 type = "critical";
0229 };
0230 };
0231 };
0232 };
0233
0234 timer {
0235 compatible = "arm,armv8-timer";
0236 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
0237 IRQ_TYPE_LEVEL_LOW)>,
0238 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
0239 IRQ_TYPE_LEVEL_LOW)>,
0240 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
0241 IRQ_TYPE_LEVEL_LOW)>,
0242 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
0243 IRQ_TYPE_LEVEL_LOW)>;
0244 };
0245
0246 pmu {
0247 compatible = "arm,cortex-a72-pmu";
0248 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0249 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0250 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
0251 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0252 interrupt-affinity = <&cpu0>,
0253 <&cpu1>,
0254 <&cpu2>,
0255 <&cpu3>;
0256 };
0257
0258 gic: interrupt-controller@1400000 {
0259 compatible = "arm,gic-400";
0260 #interrupt-cells = <3>;
0261 interrupt-controller;
0262 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
0263 <0x0 0x1420000 0 0x20000>, /* GICC */
0264 <0x0 0x1440000 0 0x20000>, /* GICH */
0265 <0x0 0x1460000 0 0x20000>; /* GICV */
0266 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
0267 IRQ_TYPE_LEVEL_LOW)>;
0268 };
0269
0270 soc: soc {
0271 compatible = "simple-bus";
0272 #address-cells = <2>;
0273 #size-cells = <2>;
0274 ranges;
0275
0276 ddr: memory-controller@1080000 {
0277 compatible = "fsl,qoriq-memory-controller";
0278 reg = <0x0 0x1080000 0x0 0x1000>;
0279 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0280 big-endian;
0281 };
0282
0283 ifc: memory-controller@1530000 {
0284 compatible = "fsl,ifc";
0285 reg = <0x0 0x1530000 0x0 0x10000>;
0286 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0287 status = "disabled";
0288 };
0289
0290 qspi: spi@1550000 {
0291 compatible = "fsl,ls1021a-qspi";
0292 #address-cells = <1>;
0293 #size-cells = <0>;
0294 reg = <0x0 0x1550000 0x0 0x10000>,
0295 <0x0 0x40000000 0x0 0x10000000>;
0296 reg-names = "QuadSPI", "QuadSPI-memory";
0297 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0298 clock-names = "qspi_en", "qspi";
0299 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0300 QORIQ_CLK_PLL_DIV(2)>,
0301 <&clockgen QORIQ_CLK_PLATFORM_PLL
0302 QORIQ_CLK_PLL_DIV(2)>;
0303 status = "disabled";
0304 };
0305
0306 esdhc: esdhc@1560000 {
0307 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
0308 reg = <0x0 0x1560000 0x0 0x10000>;
0309 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0310 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
0311 voltage-ranges = <1800 1800 3300 3300>;
0312 sdhci,auto-cmd12;
0313 big-endian;
0314 bus-width = <4>;
0315 };
0316
0317 scfg: scfg@1570000 {
0318 compatible = "fsl,ls1046a-scfg", "syscon";
0319 reg = <0x0 0x1570000 0x0 0x10000>;
0320 big-endian;
0321 #address-cells = <1>;
0322 #size-cells = <1>;
0323 ranges = <0x0 0x0 0x1570000 0x10000>;
0324
0325 extirq: interrupt-controller@1ac {
0326 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq";
0327 #interrupt-cells = <2>;
0328 #address-cells = <0>;
0329 interrupt-controller;
0330 reg = <0x1ac 4>;
0331 interrupt-map =
0332 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0333 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0334 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0335 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0336 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0337 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0338 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0339 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0340 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0341 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0342 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
0343 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0344 interrupt-map-mask = <0xf 0x0>;
0345 };
0346 };
0347
0348 crypto: crypto@1700000 {
0349 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
0350 "fsl,sec-v4.0";
0351 fsl,sec-era = <8>;
0352 #address-cells = <1>;
0353 #size-cells = <1>;
0354 ranges = <0x0 0x00 0x1700000 0x100000>;
0355 reg = <0x00 0x1700000 0x0 0x100000>;
0356 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0357 dma-coherent;
0358
0359 sec_jr0: jr@10000 {
0360 compatible = "fsl,sec-v5.4-job-ring",
0361 "fsl,sec-v5.0-job-ring",
0362 "fsl,sec-v4.0-job-ring";
0363 reg = <0x10000 0x10000>;
0364 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0365 };
0366
0367 sec_jr1: jr@20000 {
0368 compatible = "fsl,sec-v5.4-job-ring",
0369 "fsl,sec-v5.0-job-ring",
0370 "fsl,sec-v4.0-job-ring";
0371 reg = <0x20000 0x10000>;
0372 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0373 };
0374
0375 sec_jr2: jr@30000 {
0376 compatible = "fsl,sec-v5.4-job-ring",
0377 "fsl,sec-v5.0-job-ring",
0378 "fsl,sec-v4.0-job-ring";
0379 reg = <0x30000 0x10000>;
0380 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0381 };
0382
0383 sec_jr3: jr@40000 {
0384 compatible = "fsl,sec-v5.4-job-ring",
0385 "fsl,sec-v5.0-job-ring",
0386 "fsl,sec-v4.0-job-ring";
0387 reg = <0x40000 0x10000>;
0388 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0389 };
0390 };
0391
0392 qman: qman@1880000 {
0393 compatible = "fsl,qman";
0394 reg = <0x0 0x1880000 0x0 0x10000>;
0395 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0396 memory-region = <&qman_fqd &qman_pfdr>;
0397
0398 };
0399
0400 bman: bman@1890000 {
0401 compatible = "fsl,bman";
0402 reg = <0x0 0x1890000 0x0 0x10000>;
0403 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0404 memory-region = <&bman_fbpr>;
0405
0406 };
0407
0408 qportals: qman-portals@500000000 {
0409 ranges = <0x0 0x5 0x00000000 0x8000000>;
0410 };
0411
0412 bportals: bman-portals@508000000 {
0413 ranges = <0x0 0x5 0x08000000 0x8000000>;
0414 };
0415
0416 sfp: efuse@1e80000 {
0417 compatible = "fsl,ls1021a-sfp";
0418 reg = <0x0 0x1e80000 0x0 0x10000>;
0419 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0420 QORIQ_CLK_PLL_DIV(4)>;
0421 clock-names = "sfp";
0422 };
0423
0424 dcfg: dcfg@1ee0000 {
0425 compatible = "fsl,ls1046a-dcfg", "syscon";
0426 reg = <0x0 0x1ee0000 0x0 0x1000>;
0427 big-endian;
0428 };
0429
0430 clockgen: clocking@1ee1000 {
0431 compatible = "fsl,ls1046a-clockgen";
0432 reg = <0x0 0x1ee1000 0x0 0x1000>;
0433 #clock-cells = <2>;
0434 clocks = <&sysclk>;
0435 };
0436
0437 tmu: tmu@1f00000 {
0438 compatible = "fsl,qoriq-tmu";
0439 reg = <0x0 0x1f00000 0x0 0x10000>;
0440 interrupts = <0 33 0x4>;
0441 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
0442 fsl,tmu-calibration =
0443 /* Calibration data group 1 */
0444 <0x00000000 0x00000023
0445 0x00000001 0x00000029
0446 0x00000002 0x0000002f
0447 0x00000003 0x00000036
0448 0x00000004 0x0000003c
0449 0x00000005 0x00000042
0450 0x00000006 0x00000049
0451 0x00000007 0x0000004f
0452 0x00000008 0x00000055
0453 0x00000009 0x0000005c
0454 0x0000000a 0x00000062
0455 0x0000000b 0x00000068
0456 /* Calibration data group 2 */
0457 0x00010000 0x00000022
0458 0x00010001 0x0000002a
0459 0x00010002 0x00000032
0460 0x00010003 0x0000003a
0461 0x00010004 0x00000042
0462 0x00010005 0x0000004a
0463 0x00010006 0x00000052
0464 0x00010007 0x0000005a
0465 0x00010008 0x00000062
0466 0x00010009 0x0000006a
0467 /* Calibration data group 3 */
0468 0x00020000 0x00000021
0469 0x00020001 0x0000002b
0470 0x00020002 0x00000035
0471 0x00020003 0x0000003e
0472 0x00020004 0x00000048
0473 0x00020005 0x00000052
0474 0x00020006 0x0000005c
0475 /* Calibration data group 4 */
0476 0x00030000 0x00000011
0477 0x00030001 0x0000001a
0478 0x00030002 0x00000024
0479 0x00030003 0x0000002e
0480 0x00030004 0x00000038
0481 0x00030005 0x00000042
0482 0x00030006 0x0000004c
0483 0x00030007 0x00000056>;
0484 big-endian;
0485 #thermal-sensor-cells = <1>;
0486 };
0487
0488 dspi: spi@2100000 {
0489 compatible = "fsl,ls1021a-v1.0-dspi";
0490 #address-cells = <1>;
0491 #size-cells = <0>;
0492 reg = <0x0 0x2100000 0x0 0x10000>;
0493 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0494 clock-names = "dspi";
0495 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0496 QORIQ_CLK_PLL_DIV(2)>;
0497 spi-num-chipselects = <5>;
0498 big-endian;
0499 status = "disabled";
0500 };
0501
0502 i2c0: i2c@2180000 {
0503 compatible = "fsl,vf610-i2c";
0504 #address-cells = <1>;
0505 #size-cells = <0>;
0506 reg = <0x0 0x2180000 0x0 0x10000>;
0507 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0508 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0509 QORIQ_CLK_PLL_DIV(2)>;
0510 dmas = <&edma0 1 38>,
0511 <&edma0 1 39>;
0512 dma-names = "rx", "tx";
0513 status = "disabled";
0514 };
0515
0516 i2c1: i2c@2190000 {
0517 compatible = "fsl,vf610-i2c";
0518 #address-cells = <1>;
0519 #size-cells = <0>;
0520 reg = <0x0 0x2190000 0x0 0x10000>;
0521 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0522 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0523 QORIQ_CLK_PLL_DIV(2)>;
0524 status = "disabled";
0525 };
0526
0527 i2c2: i2c@21a0000 {
0528 compatible = "fsl,vf610-i2c";
0529 #address-cells = <1>;
0530 #size-cells = <0>;
0531 reg = <0x0 0x21a0000 0x0 0x10000>;
0532 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0533 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0534 QORIQ_CLK_PLL_DIV(2)>;
0535 status = "disabled";
0536 };
0537
0538 i2c3: i2c@21b0000 {
0539 compatible = "fsl,vf610-i2c";
0540 #address-cells = <1>;
0541 #size-cells = <0>;
0542 reg = <0x0 0x21b0000 0x0 0x10000>;
0543 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0544 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0545 QORIQ_CLK_PLL_DIV(2)>;
0546 status = "disabled";
0547 };
0548
0549 duart0: serial@21c0500 {
0550 compatible = "fsl,ns16550", "ns16550a";
0551 reg = <0x00 0x21c0500 0x0 0x100>;
0552 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0553 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0554 QORIQ_CLK_PLL_DIV(2)>;
0555 status = "disabled";
0556 };
0557
0558 duart1: serial@21c0600 {
0559 compatible = "fsl,ns16550", "ns16550a";
0560 reg = <0x00 0x21c0600 0x0 0x100>;
0561 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0562 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0563 QORIQ_CLK_PLL_DIV(2)>;
0564 status = "disabled";
0565 };
0566
0567 duart2: serial@21d0500 {
0568 compatible = "fsl,ns16550", "ns16550a";
0569 reg = <0x0 0x21d0500 0x0 0x100>;
0570 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0571 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0572 QORIQ_CLK_PLL_DIV(2)>;
0573 status = "disabled";
0574 };
0575
0576 duart3: serial@21d0600 {
0577 compatible = "fsl,ns16550", "ns16550a";
0578 reg = <0x0 0x21d0600 0x0 0x100>;
0579 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0580 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0581 QORIQ_CLK_PLL_DIV(2)>;
0582 status = "disabled";
0583 };
0584
0585 gpio0: gpio@2300000 {
0586 compatible = "fsl,qoriq-gpio";
0587 reg = <0x0 0x2300000 0x0 0x10000>;
0588 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0589 gpio-controller;
0590 #gpio-cells = <2>;
0591 interrupt-controller;
0592 #interrupt-cells = <2>;
0593 };
0594
0595 gpio1: gpio@2310000 {
0596 compatible = "fsl,qoriq-gpio";
0597 reg = <0x0 0x2310000 0x0 0x10000>;
0598 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0599 gpio-controller;
0600 #gpio-cells = <2>;
0601 interrupt-controller;
0602 #interrupt-cells = <2>;
0603 };
0604
0605 gpio2: gpio@2320000 {
0606 compatible = "fsl,qoriq-gpio";
0607 reg = <0x0 0x2320000 0x0 0x10000>;
0608 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0609 gpio-controller;
0610 #gpio-cells = <2>;
0611 interrupt-controller;
0612 #interrupt-cells = <2>;
0613 };
0614
0615 gpio3: gpio@2330000 {
0616 compatible = "fsl,qoriq-gpio";
0617 reg = <0x0 0x2330000 0x0 0x10000>;
0618 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0619 gpio-controller;
0620 #gpio-cells = <2>;
0621 interrupt-controller;
0622 #interrupt-cells = <2>;
0623 };
0624
0625 lpuart0: serial@2950000 {
0626 compatible = "fsl,ls1021a-lpuart";
0627 reg = <0x0 0x2950000 0x0 0x1000>;
0628 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0629 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0630 QORIQ_CLK_PLL_DIV(1)>;
0631 clock-names = "ipg";
0632 status = "disabled";
0633 };
0634
0635 lpuart1: serial@2960000 {
0636 compatible = "fsl,ls1021a-lpuart";
0637 reg = <0x0 0x2960000 0x0 0x1000>;
0638 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0639 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0640 QORIQ_CLK_PLL_DIV(2)>;
0641 clock-names = "ipg";
0642 status = "disabled";
0643 };
0644
0645 lpuart2: serial@2970000 {
0646 compatible = "fsl,ls1021a-lpuart";
0647 reg = <0x0 0x2970000 0x0 0x1000>;
0648 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0649 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0650 QORIQ_CLK_PLL_DIV(2)>;
0651 clock-names = "ipg";
0652 status = "disabled";
0653 };
0654
0655 lpuart3: serial@2980000 {
0656 compatible = "fsl,ls1021a-lpuart";
0657 reg = <0x0 0x2980000 0x0 0x1000>;
0658 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0659 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0660 QORIQ_CLK_PLL_DIV(2)>;
0661 clock-names = "ipg";
0662 status = "disabled";
0663 };
0664
0665 lpuart4: serial@2990000 {
0666 compatible = "fsl,ls1021a-lpuart";
0667 reg = <0x0 0x2990000 0x0 0x1000>;
0668 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0669 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0670 QORIQ_CLK_PLL_DIV(2)>;
0671 clock-names = "ipg";
0672 status = "disabled";
0673 };
0674
0675 lpuart5: serial@29a0000 {
0676 compatible = "fsl,ls1021a-lpuart";
0677 reg = <0x0 0x29a0000 0x0 0x1000>;
0678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0679 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0680 QORIQ_CLK_PLL_DIV(2)>;
0681 clock-names = "ipg";
0682 status = "disabled";
0683 };
0684
0685 wdog0: watchdog@2ad0000 {
0686 compatible = "fsl,imx21-wdt";
0687 reg = <0x0 0x2ad0000 0x0 0x10000>;
0688 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0689 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0690 QORIQ_CLK_PLL_DIV(2)>;
0691 big-endian;
0692 };
0693
0694 edma0: dma-controller@2c00000 {
0695 #dma-cells = <2>;
0696 compatible = "fsl,vf610-edma";
0697 reg = <0x0 0x2c00000 0x0 0x10000>,
0698 <0x0 0x2c10000 0x0 0x10000>,
0699 <0x0 0x2c20000 0x0 0x10000>;
0700 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0701 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0702 interrupt-names = "edma-tx", "edma-err";
0703 dma-channels = <32>;
0704 big-endian;
0705 clock-names = "dmamux0", "dmamux1";
0706 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0707 QORIQ_CLK_PLL_DIV(2)>,
0708 <&clockgen QORIQ_CLK_PLATFORM_PLL
0709 QORIQ_CLK_PLL_DIV(2)>;
0710 };
0711
0712 usb0: usb@2f00000 {
0713 compatible = "snps,dwc3";
0714 reg = <0x0 0x2f00000 0x0 0x10000>;
0715 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0716 dr_mode = "host";
0717 snps,quirk-frame-length-adjustment = <0x20>;
0718 snps,dis_rxdet_inp3_quirk;
0719 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0720 };
0721
0722 usb1: usb@3000000 {
0723 compatible = "snps,dwc3";
0724 reg = <0x0 0x3000000 0x0 0x10000>;
0725 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0726 dr_mode = "host";
0727 snps,quirk-frame-length-adjustment = <0x20>;
0728 snps,dis_rxdet_inp3_quirk;
0729 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0730 };
0731
0732 usb2: usb@3100000 {
0733 compatible = "snps,dwc3";
0734 reg = <0x0 0x3100000 0x0 0x10000>;
0735 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0736 dr_mode = "host";
0737 snps,quirk-frame-length-adjustment = <0x20>;
0738 snps,dis_rxdet_inp3_quirk;
0739 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
0740 };
0741
0742 sata: sata@3200000 {
0743 compatible = "fsl,ls1046a-ahci";
0744 reg = <0x0 0x3200000 0x0 0x10000>,
0745 <0x0 0x20140520 0x0 0x4>;
0746 reg-names = "ahci", "sata-ecc";
0747 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0748 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
0749 QORIQ_CLK_PLL_DIV(2)>;
0750 };
0751
0752 msi1: msi-controller@1580000 {
0753 compatible = "fsl,ls1046a-msi";
0754 msi-controller;
0755 reg = <0x0 0x1580000 0x0 0x10000>;
0756 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0757 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0758 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0759 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0760 };
0761
0762 msi2: msi-controller@1590000 {
0763 compatible = "fsl,ls1046a-msi";
0764 msi-controller;
0765 reg = <0x0 0x1590000 0x0 0x10000>;
0766 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0767 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0768 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0769 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0770 };
0771
0772 msi3: msi-controller@15a0000 {
0773 compatible = "fsl,ls1046a-msi";
0774 msi-controller;
0775 reg = <0x0 0x15a0000 0x0 0x10000>;
0776 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0777 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0778 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
0779 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0780 };
0781
0782 pcie1: pcie@3400000 {
0783 compatible = "fsl,ls1046a-pcie";
0784 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
0785 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
0786 reg-names = "regs", "config";
0787 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0788 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
0789 interrupt-names = "aer", "pme";
0790 #address-cells = <3>;
0791 #size-cells = <2>;
0792 device_type = "pci";
0793 dma-coherent;
0794 num-viewport = <8>;
0795 bus-range = <0x0 0xff>;
0796 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
0797 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0798 msi-parent = <&msi1>, <&msi2>, <&msi3>;
0799 #interrupt-cells = <1>;
0800 interrupt-map-mask = <0 0 0 7>;
0801 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0802 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0803 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0804 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0805 status = "disabled";
0806 };
0807
0808 pcie_ep1: pcie_ep@3400000 {
0809 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
0810 reg = <0x00 0x03400000 0x0 0x00100000>,
0811 <0x40 0x00000000 0x8 0x00000000>;
0812 reg-names = "regs", "addr_space";
0813 num-ib-windows = <6>;
0814 num-ob-windows = <8>;
0815 status = "disabled";
0816 };
0817
0818 pcie2: pcie@3500000 {
0819 compatible = "fsl,ls1046a-pcie";
0820 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
0821 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
0822 reg-names = "regs", "config";
0823 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0824 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
0825 interrupt-names = "aer", "pme";
0826 #address-cells = <3>;
0827 #size-cells = <2>;
0828 device_type = "pci";
0829 dma-coherent;
0830 num-viewport = <8>;
0831 bus-range = <0x0 0xff>;
0832 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
0833 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0834 msi-parent = <&msi2>, <&msi3>, <&msi1>;
0835 #interrupt-cells = <1>;
0836 interrupt-map-mask = <0 0 0 7>;
0837 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0838 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0839 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0840 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0841 status = "disabled";
0842 };
0843
0844 pcie_ep2: pcie_ep@3500000 {
0845 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
0846 reg = <0x00 0x03500000 0x0 0x00100000>,
0847 <0x48 0x00000000 0x8 0x00000000>;
0848 reg-names = "regs", "addr_space";
0849 num-ib-windows = <6>;
0850 num-ob-windows = <8>;
0851 status = "disabled";
0852 };
0853
0854 pcie3: pcie@3600000 {
0855 compatible = "fsl,ls1046a-pcie";
0856 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
0857 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
0858 reg-names = "regs", "config";
0859 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0860 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
0861 interrupt-names = "aer", "pme";
0862 #address-cells = <3>;
0863 #size-cells = <2>;
0864 device_type = "pci";
0865 dma-coherent;
0866 num-viewport = <8>;
0867 bus-range = <0x0 0xff>;
0868 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
0869 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0870 msi-parent = <&msi3>, <&msi1>, <&msi2>;
0871 #interrupt-cells = <1>;
0872 interrupt-map-mask = <0 0 0 7>;
0873 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0874 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0875 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0876 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0877 status = "disabled";
0878 };
0879
0880 pcie_ep3: pcie_ep@3600000 {
0881 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
0882 reg = <0x00 0x03600000 0x0 0x00100000>,
0883 <0x50 0x00000000 0x8 0x00000000>;
0884 reg-names = "regs", "addr_space";
0885 num-ib-windows = <6>;
0886 num-ob-windows = <8>;
0887 status = "disabled";
0888 };
0889
0890 qdma: dma-controller@8380000 {
0891 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
0892 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
0893 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
0894 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
0895 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0896 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0897 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0898 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0899 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0900 interrupt-names = "qdma-error", "qdma-queue0",
0901 "qdma-queue1", "qdma-queue2", "qdma-queue3";
0902 dma-channels = <8>;
0903 block-number = <1>;
0904 block-offset = <0x10000>;
0905 fsl,dma-queues = <2>;
0906 status-sizes = <64>;
0907 queue-sizes = <64 64>;
0908 big-endian;
0909 };
0910
0911 rcpm: power-controller@1ee2140 {
0912 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
0913 reg = <0x0 0x1ee2140 0x0 0x4>;
0914 #fsl,rcpm-wakeup-cells = <1>;
0915 };
0916
0917 ftm_alarm0: timer@29d0000 {
0918 compatible = "fsl,ls1046a-ftm-alarm";
0919 reg = <0x0 0x29d0000 0x0 0x10000>;
0920 fsl,rcpm-wakeup = <&rcpm 0x20000>;
0921 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0922 big-endian;
0923 };
0924 };
0925
0926 reserved-memory {
0927 #address-cells = <2>;
0928 #size-cells = <2>;
0929 ranges;
0930
0931 bman_fbpr: bman-fbpr {
0932 compatible = "shared-dma-pool";
0933 size = <0 0x1000000>;
0934 alignment = <0 0x1000000>;
0935 no-map;
0936 };
0937
0938 qman_fqd: qman-fqd {
0939 compatible = "shared-dma-pool";
0940 size = <0 0x800000>;
0941 alignment = <0 0x800000>;
0942 no-map;
0943 };
0944
0945 qman_pfdr: qman-pfdr {
0946 compatible = "shared-dma-pool";
0947 size = <0 0x2000000>;
0948 alignment = <0 0x2000000>;
0949 no-map;
0950 };
0951 };
0952
0953 firmware {
0954 optee {
0955 compatible = "linaro,optee-tz";
0956 method = "smc";
0957 };
0958 };
0959 };
0960
0961 #include "qoriq-qman-portals.dtsi"
0962 #include "qoriq-bman-portals.dtsi"
