dts/freescale/fsl-ls1046a-frwy.dts

0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
0004  *
0005  * Copyright 2019 NXP.
0006  *
0007  */
0008
0009 /dts-v1/;
0010
0011 #include "fsl-ls1046a.dtsi"
0012
0013 / {
0014         model = "LS1046A FRWY Board";
0015         compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";
0016
0017         aliases {
0018                 serial0 = &duart0;
0019                 serial1 = &duart1;
0020                 serial2 = &duart2;
0021                 serial3 = &duart3;
0022         };
0023
0024         chosen {
0025                 stdout-path = "serial0:115200n8";
0026         };
0027
0028         sb_3v3: regulator-sb3v3 {
0029                 compatible = "regulator-fixed";
0030                 regulator-name = "LT8642SEV-3.3V";
0031                 regulator-min-microvolt = <3300000>;
0032                 regulator-max-microvolt = <3300000>;
0033                 regulator-boot-on;
0034                 regulator-always-on;
0035         };
0036 };
0037
0038 &duart0 {
0039         status = "okay";
0040 };
0041
0042 &duart1 {
0043         status = "okay";
0044 };
0045
0046 &duart2 {
0047         status = "okay";
0048 };
0049
0050 &duart3 {
0051         status = "okay";
0052 };
0053
0054 &i2c0 {
0055         status = "okay";
0056
0057         i2c-mux@77 {
0058                 compatible = "nxp,pca9546";
0059                 reg = <0x77>;
0060                 #address-cells = <1>;
0061                 #size-cells = <0>;
0062
0063                 i2c@0 {
0064                         #address-cells = <1>;
0065                         #size-cells = <0>;
0066                         reg = <0>;
0067
0068                         power-monitor@40 {
0069                                 compatible = "ti,ina220";
0070                                 reg = <0x40>;
0071                                 shunt-resistor = <1000>;
0072                         };
0073
0074                         temperature-sensor@4c {
0075                                 compatible = "nxp,sa56004";
0076                                 reg = <0x4c>;
0077                                 vcc-supply = <&sb_3v3>;
0078                         };
0079
0080                         rtc@51 {
0081                                 compatible = "nxp,pcf2129";
0082                                 reg = <0x51>;
0083                         };
0084
0085                         eeprom@52 {
0086                                 compatible = "onnn,cat24c04", "atmel,24c04";
0087                                 reg = <0x52>;
0088                         };
0089                 };
0090         };
0091 };
0092
0093 &ifc {
0094         #address-cells = <2>;
0095         #size-cells = <1>;
0096         /* NAND Flash */
0097         ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
0098         status = "okay";
0099
0100         nand@0,0 {
0101                 compatible = "fsl,ifc-nand";
0102                 #address-cells = <1>;
0103                 #size-cells = <1>;
0104                 reg = <0x0 0x0 0x10000>;
0105         };
0106
0107 };
0108
0109 &qspi {
0110         status = "okay";
0111
0112         mt25qu512a0: flash@0 {
0113                 compatible = "jedec,spi-nor";
0114                 #address-cells = <1>;
0115                 #size-cells = <1>;
0116                 spi-max-frequency = <50000000>;
0117                 spi-rx-bus-width = <4>;
0118                 spi-tx-bus-width = <1>;
0119                 reg = <0>;
0120         };
0121 };
0122
0123 #include "fsl-ls1046-post.dtsi"
0124
0125 &fman0 {
0126         ethernet@e0000 {
0127                 phy-handle = <&qsgmii_phy4>;
0128                 phy-connection-type = "qsgmii";
0129         };
0130
0131         ethernet@e8000 {
0132                 phy-handle = <&qsgmii_phy2>;
0133                 phy-connection-type = "qsgmii";
0134         };
0135
0136         ethernet@ea000 {
0137                 phy-handle = <&qsgmii_phy1>;
0138                 phy-connection-type = "qsgmii";
0139         };
0140
0141         ethernet@f2000 {
0142                 phy-handle = <&qsgmii_phy3>;
0143                 phy-connection-type = "qsgmii";
0144         };
0145
0146         mdio@fd000 {
0147                 qsgmii_phy1: ethernet-phy@1c {
0148                         reg = <0x1c>;
0149                 };
0150
0151                 qsgmii_phy2: ethernet-phy@1d {
0152                         reg = <0x1d>;
0153                 };
0154
0155                 qsgmii_phy3: ethernet-phy@1e {
0156                         reg = <0x1e>;
0157                 };
0158
0159                 qsgmii_phy4: ethernet-phy@1f {
0160                         reg = <0x1f>;
0161                 };
0162         };
0163 };