dts/exynos/exynos-pinctrl.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Samsung Exynos DTS pinctrl constants
0004  *
0005  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
0006  *      http://www.samsung.com
0007  * Copyright (c) 2022 Linaro Ltd
0008  * Author: Krzysztof Kozlowski <krzk@kernel.org>
0009  */
0010
0011 #ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
0012 #define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
0013
0014 #define EXYNOS_PIN_PULL_NONE        0
0015 #define EXYNOS_PIN_PULL_DOWN        1
0016 #define EXYNOS_PIN_PULL_UP      3
0017
0018 /* Pin function in power down mode */
0019 #define EXYNOS_PIN_PDN_OUT0     0
0020 #define EXYNOS_PIN_PDN_OUT1     1
0021 #define EXYNOS_PIN_PDN_INPUT        2
0022 #define EXYNOS_PIN_PDN_PREV     3
0023
0024 /*
0025  * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850
0026  * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
0027  */
0028 #define EXYNOS5420_PIN_DRV_LV1      0
0029 #define EXYNOS5420_PIN_DRV_LV2      1
0030 #define EXYNOS5420_PIN_DRV_LV3      2
0031 #define EXYNOS5420_PIN_DRV_LV4      3
0032
0033 /* Drive strengths for Exynos5433 */
0034 #define EXYNOS5433_PIN_DRV_FAST_SR1 0
0035 #define EXYNOS5433_PIN_DRV_FAST_SR2 1
0036 #define EXYNOS5433_PIN_DRV_FAST_SR3 2
0037 #define EXYNOS5433_PIN_DRV_FAST_SR4 3
0038 #define EXYNOS5433_PIN_DRV_FAST_SR5 4
0039 #define EXYNOS5433_PIN_DRV_FAST_SR6 5
0040 #define EXYNOS5433_PIN_DRV_SLOW_SR1 8
0041 #define EXYNOS5433_PIN_DRV_SLOW_SR2 9
0042 #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
0043 #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
0044 #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
0045 #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
0046
0047 /* Drive strengths for Exynos7 (except FSYS1) */
0048 #define EXYNOS7_PIN_DRV_LV1     0
0049 #define EXYNOS7_PIN_DRV_LV2     2
0050 #define EXYNOS7_PIN_DRV_LV3     1
0051 #define EXYNOS7_PIN_DRV_LV4     3
0052
0053 /* Drive strengths for Exynos7 FSYS1 block */
0054 #define EXYNOS7_FSYS1_PIN_DRV_LV1   0
0055 #define EXYNOS7_FSYS1_PIN_DRV_LV2   4
0056 #define EXYNOS7_FSYS1_PIN_DRV_LV3   2
0057 #define EXYNOS7_FSYS1_PIN_DRV_LV4   6
0058 #define EXYNOS7_FSYS1_PIN_DRV_LV5   1
0059 #define EXYNOS7_FSYS1_PIN_DRV_LV6   5
0060
0061 /* Drive strengths for Exynos850 GPIO_HSI block */
0062 #define EXYNOS850_HSI_PIN_DRV_LV1   0   /* 1x   */
0063 #define EXYNOS850_HSI_PIN_DRV_LV1_5 1   /* 1.5x */
0064 #define EXYNOS850_HSI_PIN_DRV_LV2   2   /* 2x   */
0065 #define EXYNOS850_HSI_PIN_DRV_LV2_5 3   /* 2.5x */
0066 #define EXYNOS850_HSI_PIN_DRV_LV3   4   /* 3x   */
0067 #define EXYNOS850_HSI_PIN_DRV_LV4   5   /* 4x   */
0068
0069 #define EXYNOS_PIN_FUNC_INPUT       0
0070 #define EXYNOS_PIN_FUNC_OUTPUT      1
0071 #define EXYNOS_PIN_FUNC_2       2
0072 #define EXYNOS_PIN_FUNC_3       3
0073 #define EXYNOS_PIN_FUNC_4       4
0074 #define EXYNOS_PIN_FUNC_5       5
0075 #define EXYNOS_PIN_FUNC_6       6
0076 #define EXYNOS_PIN_FUNC_EINT        0xf
0077 #define EXYNOS_PIN_FUNC_F       EXYNOS_PIN_FUNC_EINT
0078
0079 #endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */