0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Broadcom Ltd.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008
0009 / {
0010 compatible = "brcm,bcm6858", "brcm,bcmbca";
0011 #address-cells = <2>;
0012 #size-cells = <2>;
0013
0014 interrupt-parent = <&gic>;
0015
0016 cpus {
0017 #address-cells = <2>;
0018 #size-cells = <0>;
0019
0020 B53_0: cpu@0 {
0021 compatible = "brcm,brahma-b53";
0022 device_type = "cpu";
0023 reg = <0x0 0x0>;
0024 next-level-cache = <&L2_0>;
0025 enable-method = "psci";
0026 };
0027
0028 B53_1: cpu@1 {
0029 compatible = "brcm,brahma-b53";
0030 device_type = "cpu";
0031 reg = <0x0 0x1>;
0032 next-level-cache = <&L2_0>;
0033 enable-method = "psci";
0034 };
0035
0036 B53_2: cpu@2 {
0037 compatible = "brcm,brahma-b53";
0038 device_type = "cpu";
0039 reg = <0x0 0x2>;
0040 next-level-cache = <&L2_0>;
0041 enable-method = "psci";
0042 };
0043
0044 B53_3: cpu@3 {
0045 compatible = "brcm,brahma-b53";
0046 device_type = "cpu";
0047 reg = <0x0 0x3>;
0048 next-level-cache = <&L2_0>;
0049 enable-method = "psci";
0050 };
0051 L2_0: l2-cache0 {
0052 compatible = "cache";
0053 };
0054 };
0055
0056 timer {
0057 compatible = "arm,armv8-timer";
0058 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0059 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0060 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0061 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0062 };
0063
0064 pmu: pmu {
0065 compatible = "arm,armv8-pmuv3";
0066 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0067 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0068 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0069 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0070 interrupt-affinity = <&B53_0>, <&B53_1>,
0071 <&B53_2>, <&B53_3>;
0072 };
0073
0074 clocks: clocks {
0075 periph_clk:periph-clk {
0076 compatible = "fixed-clock";
0077 #clock-cells = <0>;
0078 clock-frequency = <200000000>;
0079 };
0080 };
0081
0082 psci {
0083 compatible = "arm,psci-0.2";
0084 method = "smc";
0085 };
0086
0087 axi@81000000 {
0088 compatible = "simple-bus";
0089 #address-cells = <1>;
0090 #size-cells = <1>;
0091 ranges = <0x0 0x0 0x81000000 0x8000>;
0092
0093 gic: interrupt-controller@1000 {
0094 compatible = "arm,gic-400";
0095 #interrupt-cells = <3>;
0096 interrupt-controller;
0097 reg = <0x1000 0x1000>, /* GICD */
0098 <0x2000 0x2000>, /* GICC */
0099 <0x4000 0x2000>, /* GICH */
0100 <0x6000 0x2000>; /* GICV */
0101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
0102 IRQ_TYPE_LEVEL_HIGH)>;
0103 };
0104 };
0105
0106 bus@ff800000 {
0107 compatible = "simple-bus";
0108 #address-cells = <1>;
0109 #size-cells = <1>;
0110 ranges = <0x0 0x0 0xff800000 0x62000>;
0111
0112 uart0: serial@640 {
0113 compatible = "brcm,bcm6345-uart";
0114 reg = <0x640 0x18>;
0115 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0116 clocks = <&periph_clk>;
0117 clock-names = "refclk";
0118 status = "disabled";
0119 };
0120 };
0121 };
