0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Fast Models
0004 *
0005 * Architecture Envelope Model (AEM) ARMv8-A
0006 * ARMAEMv8AMPCT
0007 *
0008 * RTSM_VE_AEMv8A.lisa
0009 */
0010
0011 /dts-v1/;
0012
0013 #include <dt-bindings/interrupt-controller/arm-gic.h>
0014
0015 /memreserve/ 0x80000000 0x00010000;
0016
0017 #include "rtsm_ve-motherboard.dtsi"
0018
0019 / {
0020 model = "RTSM_VE_AEMv8A";
0021 compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
0022 interrupt-parent = <&gic>;
0023 #address-cells = <2>;
0024 #size-cells = <2>;
0025
0026 chosen { };
0027
0028 aliases {
0029 serial0 = &v2m_serial0;
0030 serial1 = &v2m_serial1;
0031 serial2 = &v2m_serial2;
0032 serial3 = &v2m_serial3;
0033 };
0034
0035 cpus {
0036 #address-cells = <2>;
0037 #size-cells = <0>;
0038
0039 cpu@0 {
0040 device_type = "cpu";
0041 compatible = "arm,armv8";
0042 reg = <0x0 0x0>;
0043 enable-method = "spin-table";
0044 cpu-release-addr = <0x0 0x8000fff8>;
0045 next-level-cache = <&L2_0>;
0046 };
0047 cpu@1 {
0048 device_type = "cpu";
0049 compatible = "arm,armv8";
0050 reg = <0x0 0x1>;
0051 enable-method = "spin-table";
0052 cpu-release-addr = <0x0 0x8000fff8>;
0053 next-level-cache = <&L2_0>;
0054 };
0055 cpu@2 {
0056 device_type = "cpu";
0057 compatible = "arm,armv8";
0058 reg = <0x0 0x2>;
0059 enable-method = "spin-table";
0060 cpu-release-addr = <0x0 0x8000fff8>;
0061 next-level-cache = <&L2_0>;
0062 };
0063 cpu@3 {
0064 device_type = "cpu";
0065 compatible = "arm,armv8";
0066 reg = <0x0 0x3>;
0067 enable-method = "spin-table";
0068 cpu-release-addr = <0x0 0x8000fff8>;
0069 next-level-cache = <&L2_0>;
0070 };
0071
0072 L2_0: l2-cache0 {
0073 compatible = "cache";
0074 };
0075 };
0076
0077 memory@80000000 {
0078 device_type = "memory";
0079 reg = <0x00000000 0x80000000 0 0x80000000>,
0080 <0x00000008 0x80000000 0 0x80000000>;
0081 };
0082
0083 reserved-memory {
0084 #address-cells = <2>;
0085 #size-cells = <2>;
0086 ranges;
0087
0088 /* Chipselect 2,00000000 is physically at 0x18000000 */
0089 vram: vram@18000000 {
0090 /* 8 MB of designated video RAM */
0091 compatible = "shared-dma-pool";
0092 reg = <0x00000000 0x18000000 0 0x00800000>;
0093 no-map;
0094 };
0095 };
0096
0097 gic: interrupt-controller@2c001000 {
0098 compatible = "arm,gic-400", "arm,cortex-a15-gic";
0099 #interrupt-cells = <3>;
0100 #address-cells = <0>;
0101 interrupt-controller;
0102 reg = <0x0 0x2c001000 0 0x1000>,
0103 <0x0 0x2c002000 0 0x2000>,
0104 <0x0 0x2c004000 0 0x2000>,
0105 <0x0 0x2c006000 0 0x2000>;
0106 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0107 };
0108
0109 timer {
0110 compatible = "arm,armv8-timer";
0111 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0114 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0115 clock-frequency = <100000000>;
0116 };
0117
0118 pmu {
0119 compatible = "arm,armv8-pmuv3";
0120 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0121 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
0122 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
0123 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0124 };
0125
0126 panel {
0127 compatible = "arm,rtsm-display";
0128 port {
0129 panel_in: endpoint {
0130 remote-endpoint = <&clcd_pads>;
0131 };
0132 };
0133 };
0134
0135 bus@8000000 {
0136 #interrupt-cells = <1>;
0137 interrupt-map-mask = <0 0 63>;
0138 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0139 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0140 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0141 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0142 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0143 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0144 <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0145 <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0146 <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0147 <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0148 <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0149 <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0150 <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0151 <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0152 <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0153 <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0154 <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0155 <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0156 <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0157 <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0158 <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0159 <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0160 <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0161 <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0162 <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0163 <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0164 <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0165 <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0166 <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0167 <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0168 <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0169 <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
0170 <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0171 <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0172 <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0173 <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0174 <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0175 <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0176 <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0177 <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0178 <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0179 <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0180 <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0181 };
0182 };
