OSCL-LXR |
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0001 /*
0002 * ARM Juno Platform motherboard peripherals
0003 *
0004 * Copyright (c) 2013-2014 ARM Ltd
0005 *
0006 * This file is licensed under a dual GPLv2 or BSD license.
0007 *
0008 */
0009
0010 / {
0011 mb_clk24mhz: clk24mhz {
0012 compatible = "fixed-clock";
0013 #clock-cells = <0>;
0014 clock-frequency = <24000000>;
0015 clock-output-names = "juno_mb:clk24mhz";
0016 };
0017
0018 mb_clk25mhz: clk25mhz {
0019 compatible = "fixed-clock";
0020 #clock-cells = <0>;
0021 clock-frequency = <25000000>;
0022 clock-output-names = "juno_mb:clk25mhz";
0023 };
0024
0025 v2m_refclk1mhz: refclk1mhz {
0026 compatible = "fixed-clock";
0027 #clock-cells = <0>;
0028 clock-frequency = <1000000>;
0029 clock-output-names = "juno_mb:refclk1mhz";
0030 };
0031
0032 v2m_refclk32khz: refclk32khz {
0033 compatible = "fixed-clock";
0034 #clock-cells = <0>;
0035 clock-frequency = <32768>;
0036 clock-output-names = "juno_mb:refclk32khz";
0037 };
0038
0039 mb_fixed_3v3: mcc-sb-3v3 {
0040 compatible = "regulator-fixed";
0041 regulator-name = "MCC_SB_3V3";
0042 regulator-min-microvolt = <3300000>;
0043 regulator-max-microvolt = <3300000>;
0044 regulator-always-on;
0045 };
0046
0047 gpio-keys {
0048 compatible = "gpio-keys";
0049
0050 power-button {
0051 debounce-interval = <50>;
0052 wakeup-source;
0053 linux,code = <116>;
0054 label = "POWER";
0055 gpios = <&iofpga_gpio0 0 0x4>;
0056 };
0057 home-button {
0058 debounce-interval = <50>;
0059 wakeup-source;
0060 linux,code = <102>;
0061 label = "HOME";
0062 gpios = <&iofpga_gpio0 1 0x4>;
0063 };
0064 rlock-button {
0065 debounce-interval = <50>;
0066 wakeup-source;
0067 linux,code = <152>;
0068 label = "RLOCK";
0069 gpios = <&iofpga_gpio0 2 0x4>;
0070 };
0071 vol-up-button {
0072 debounce-interval = <50>;
0073 wakeup-source;
0074 linux,code = <115>;
0075 label = "VOL+";
0076 gpios = <&iofpga_gpio0 3 0x4>;
0077 };
0078 vol-down-button {
0079 debounce-interval = <50>;
0080 wakeup-source;
0081 linux,code = <114>;
0082 label = "VOL-";
0083 gpios = <&iofpga_gpio0 4 0x4>;
0084 };
0085 nmi-button {
0086 debounce-interval = <50>;
0087 wakeup-source;
0088 linux,code = <99>;
0089 label = "NMI";
0090 gpios = <&iofpga_gpio0 5 0x4>;
0091 };
0092 };
0093
0094 bus@8000000 {
0095 compatible = "simple-bus";
0096 #address-cells = <2>;
0097 #size-cells = <1>;
0098 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
0099
0100 motherboard-bus@8000000 {
0101 compatible = "arm,vexpress,v2p-p1", "simple-bus";
0102 #address-cells = <2>; /* SMB chipselect number and offset */
0103 #size-cells = <1>;
0104 ranges = <0 0 0 0x08000000 0x04000000>,
0105 <1 0 0 0x14000000 0x04000000>,
0106 <2 0 0 0x18000000 0x04000000>,
0107 <3 0 0 0x1c000000 0x04000000>,
0108 <4 0 0 0x0c000000 0x04000000>,
0109 <5 0 0 0x10000000 0x04000000>;
0110 arm,hbi = <0x252>;
0111 arm,vexpress,site = <0>;
0112
0113 flash@0 {
0114 /* 2 * 32MiB NOR Flash memory mounted on CS0 */
0115 compatible = "arm,vexpress-flash", "cfi-flash";
0116 reg = <0 0x00000000 0x04000000>;
0117 bank-width = <4>;
0118 /*
0119 * Unfortunately, accessing the flash disturbs
0120 * the CPU idle states (suspend) and CPU
0121 * hotplug of the platform. For this reason,
0122 * flash hardware access is disabled by default.
0123 */
0124 status = "disabled";
0125 partitions {
0126 compatible = "arm,arm-firmware-suite";
0127 };
0128 };
0129
0130 ethernet@200000000 {
0131 compatible = "smsc,lan9118", "smsc,lan9115";
0132 reg = <2 0x00000000 0x10000>;
0133 interrupts = <3>;
0134 phy-mode = "mii";
0135 reg-io-width = <4>;
0136 smsc,irq-active-high;
0137 smsc,irq-push-pull;
0138 clocks = <&mb_clk25mhz>;
0139 vdd33a-supply = <&mb_fixed_3v3>;
0140 vddvario-supply = <&mb_fixed_3v3>;
0141 };
0142
0143 iofpga-bus@300000000 {
0144 compatible = "simple-bus";
0145 #address-cells = <1>;
0146 #size-cells = <1>;
0147 ranges = <0 3 0 0x200000>;
0148
0149 v2m_sysctl: sysctl@20000 {
0150 compatible = "arm,sp810", "arm,primecell";
0151 reg = <0x020000 0x1000>;
0152 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
0153 clock-names = "refclk", "timclk", "apb_pclk";
0154 #clock-cells = <1>;
0155 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
0156 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
0157 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
0158 };
0159
0160 apbregs@10000 {
0161 compatible = "syscon", "simple-mfd";
0162 reg = <0x010000 0x1000>;
0163 ranges = <0x0 0x10000 0x1000>;
0164 #address-cells = <1>;
0165 #size-cells = <1>;
0166
0167 led@8,0 {
0168 compatible = "register-bit-led";
0169 reg = <0x08 0x04>;
0170 offset = <0x08>;
0171 mask = <0x01>;
0172 label = "vexpress:0";
0173 linux,default-trigger = "heartbeat";
0174 default-state = "on";
0175 };
0176 led@8,1 {
0177 compatible = "register-bit-led";
0178 reg = <0x08 0x04>;
0179 offset = <0x08>;
0180 mask = <0x02>;
0181 label = "vexpress:1";
0182 linux,default-trigger = "mmc0";
0183 default-state = "off";
0184 };
0185 led@8,2 {
0186 compatible = "register-bit-led";
0187 reg = <0x08 0x04>;
0188 offset = <0x08>;
0189 mask = <0x04>;
0190 label = "vexpress:2";
0191 linux,default-trigger = "cpu0";
0192 default-state = "off";
0193 };
0194 led@8,3 {
0195 compatible = "register-bit-led";
0196 reg = <0x08 0x04>;
0197 offset = <0x08>;
0198 mask = <0x08>;
0199 label = "vexpress:3";
0200 linux,default-trigger = "cpu1";
0201 default-state = "off";
0202 };
0203 led@8,4 {
0204 compatible = "register-bit-led";
0205 reg = <0x08 0x04>;
0206 offset = <0x08>;
0207 mask = <0x10>;
0208 label = "vexpress:4";
0209 linux,default-trigger = "cpu2";
0210 default-state = "off";
0211 };
0212 led@8,5 {
0213 compatible = "register-bit-led";
0214 reg = <0x08 0x04>;
0215 offset = <0x08>;
0216 mask = <0x20>;
0217 label = "vexpress:5";
0218 linux,default-trigger = "cpu3";
0219 default-state = "off";
0220 };
0221 led@8,6 {
0222 compatible = "register-bit-led";
0223 reg = <0x08 0x04>;
0224 offset = <0x08>;
0225 mask = <0x40>;
0226 label = "vexpress:6";
0227 default-state = "off";
0228 };
0229 led@8,7 {
0230 compatible = "register-bit-led";
0231 reg = <0x08 0x04>;
0232 offset = <0x08>;
0233 mask = <0x80>;
0234 label = "vexpress:7";
0235 default-state = "off";
0236 };
0237 };
0238
0239 mmc@50000 {
0240 compatible = "arm,pl180", "arm,primecell";
0241 reg = <0x050000 0x1000>;
0242 interrupts = <5>;
0243 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
0244 wp-gpios = <&v2m_mmc_gpios 1 0>; */
0245 max-frequency = <12000000>;
0246 vmmc-supply = <&mb_fixed_3v3>;
0247 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
0248 clock-names = "mclk", "apb_pclk";
0249 };
0250
0251 kmi@60000 {
0252 compatible = "arm,pl050", "arm,primecell";
0253 reg = <0x060000 0x1000>;
0254 interrupts = <8>;
0255 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
0256 clock-names = "KMIREFCLK", "apb_pclk";
0257 };
0258
0259 kmi@70000 {
0260 compatible = "arm,pl050", "arm,primecell";
0261 reg = <0x070000 0x1000>;
0262 interrupts = <8>;
0263 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
0264 clock-names = "KMIREFCLK", "apb_pclk";
0265 };
0266
0267 watchdog@f0000 {
0268 compatible = "arm,sp805", "arm,primecell";
0269 reg = <0x0f0000 0x10000>;
0270 interrupts = <7>;
0271 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
0272 clock-names = "wdog_clk", "apb_pclk";
0273 };
0274
0275 v2m_timer01: timer@110000 {
0276 compatible = "arm,sp804", "arm,primecell";
0277 reg = <0x110000 0x10000>;
0278 interrupts = <9>;
0279 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
0280 clock-names = "timclken1", "timclken2", "apb_pclk";
0281 };
0282
0283 v2m_timer23: timer@120000 {
0284 compatible = "arm,sp804", "arm,primecell";
0285 reg = <0x120000 0x10000>;
0286 interrupts = <9>;
0287 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
0288 clock-names = "timclken1", "timclken2", "apb_pclk";
0289 };
0290
0291 rtc@170000 {
0292 compatible = "arm,pl031", "arm,primecell";
0293 reg = <0x170000 0x10000>;
0294 interrupts = <0>;
0295 clocks = <&soc_smc50mhz>;
0296 clock-names = "apb_pclk";
0297 };
0298
0299 iofpga_gpio0: gpio@1d0000 {
0300 compatible = "arm,pl061", "arm,primecell";
0301 reg = <0x1d0000 0x1000>;
0302 interrupts = <6>;
0303 clocks = <&soc_smc50mhz>;
0304 clock-names = "apb_pclk";
0305 gpio-controller;
0306 #gpio-cells = <2>;
0307 interrupt-controller;
0308 #interrupt-cells = <2>;
0309 };
0310 };
0311 };
0312 };
0313 };
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