0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd. Fast Models
0004 *
0005 * Architecture Envelope Model (AEM) ARMv8-A
0006 * ARMAEMv8AMPCT
0007 *
0008 * FVP Base RevC
0009 */
0010
0011 /dts-v1/;
0012
0013 #include <dt-bindings/interrupt-controller/arm-gic.h>
0014
0015 /memreserve/ 0x80000000 0x00010000;
0016
0017 #include "rtsm_ve-motherboard.dtsi"
0018 #include "rtsm_ve-motherboard-rs2.dtsi"
0019
0020 / {
0021 model = "FVP Base RevC";
0022 compatible = "arm,fvp-base-revc", "arm,vexpress";
0023 interrupt-parent = <&gic>;
0024 #address-cells = <2>;
0025 #size-cells = <2>;
0026
0027 chosen { };
0028
0029 aliases {
0030 serial0 = &v2m_serial0;
0031 serial1 = &v2m_serial1;
0032 serial2 = &v2m_serial2;
0033 serial3 = &v2m_serial3;
0034 };
0035
0036 psci {
0037 compatible = "arm,psci-0.2";
0038 method = "smc";
0039 };
0040
0041 cpus {
0042 #address-cells = <2>;
0043 #size-cells = <0>;
0044
0045 cpu0: cpu@0 {
0046 device_type = "cpu";
0047 compatible = "arm,armv8";
0048 reg = <0x0 0x000>;
0049 enable-method = "psci";
0050 };
0051 cpu1: cpu@100 {
0052 device_type = "cpu";
0053 compatible = "arm,armv8";
0054 reg = <0x0 0x100>;
0055 enable-method = "psci";
0056 };
0057 cpu2: cpu@200 {
0058 device_type = "cpu";
0059 compatible = "arm,armv8";
0060 reg = <0x0 0x200>;
0061 enable-method = "psci";
0062 };
0063 cpu3: cpu@300 {
0064 device_type = "cpu";
0065 compatible = "arm,armv8";
0066 reg = <0x0 0x300>;
0067 enable-method = "psci";
0068 };
0069 cpu4: cpu@10000 {
0070 device_type = "cpu";
0071 compatible = "arm,armv8";
0072 reg = <0x0 0x10000>;
0073 enable-method = "psci";
0074 };
0075 cpu5: cpu@10100 {
0076 device_type = "cpu";
0077 compatible = "arm,armv8";
0078 reg = <0x0 0x10100>;
0079 enable-method = "psci";
0080 };
0081 cpu6: cpu@10200 {
0082 device_type = "cpu";
0083 compatible = "arm,armv8";
0084 reg = <0x0 0x10200>;
0085 enable-method = "psci";
0086 };
0087 cpu7: cpu@10300 {
0088 device_type = "cpu";
0089 compatible = "arm,armv8";
0090 reg = <0x0 0x10300>;
0091 enable-method = "psci";
0092 };
0093 };
0094
0095 memory@80000000 {
0096 device_type = "memory";
0097 reg = <0x00000000 0x80000000 0 0x80000000>,
0098 <0x00000008 0x80000000 0 0x80000000>;
0099 };
0100
0101 reserved-memory {
0102 #address-cells = <2>;
0103 #size-cells = <2>;
0104 ranges;
0105
0106 /* Chipselect 2,00000000 is physically at 0x18000000 */
0107 vram: vram@18000000 {
0108 /* 8 MB of designated video RAM */
0109 compatible = "shared-dma-pool";
0110 reg = <0x00000000 0x18000000 0 0x00800000>;
0111 no-map;
0112 };
0113 };
0114
0115 gic: interrupt-controller@2f000000 {
0116 compatible = "arm,gic-v3";
0117 #interrupt-cells = <3>;
0118 #address-cells = <2>;
0119 #size-cells = <2>;
0120 ranges;
0121 interrupt-controller;
0122 reg = <0x0 0x2f000000 0 0x10000>, // GICD
0123 <0x0 0x2f100000 0 0x200000>, // GICR
0124 <0x0 0x2c000000 0 0x2000>, // GICC
0125 <0x0 0x2c010000 0 0x2000>, // GICH
0126 <0x0 0x2c02f000 0 0x2000>; // GICV
0127 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0128
0129 its: msi-controller@2f020000 {
0130 #msi-cells = <1>;
0131 compatible = "arm,gic-v3-its";
0132 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
0133 msi-controller;
0134 };
0135 };
0136
0137 timer {
0138 compatible = "arm,armv8-timer";
0139 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0140 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0141 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0142 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0143 };
0144
0145 pmu {
0146 compatible = "arm,armv8-pmuv3";
0147 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0148 };
0149
0150 spe-pmu {
0151 compatible = "arm,statistical-profiling-extension-v1";
0152 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
0153 };
0154
0155 pci: pci@40000000 {
0156 #address-cells = <0x3>;
0157 #size-cells = <0x2>;
0158 #interrupt-cells = <0x1>;
0159 compatible = "pci-host-ecam-generic";
0160 device_type = "pci";
0161 bus-range = <0x0 0x1>;
0162 reg = <0x0 0x40000000 0x0 0x10000000>;
0163 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
0164 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0165 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
0166 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
0167 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
0168 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0169 msi-map = <0x0 &its 0x0 0x10000>;
0170 iommu-map = <0x0 &smmu 0x0 0x10000>;
0171
0172 dma-coherent;
0173 };
0174
0175 smmu: iommu@2b400000 {
0176 compatible = "arm,smmu-v3";
0177 reg = <0x0 0x2b400000 0x0 0x100000>;
0178 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
0179 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
0180 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
0181 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
0182 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
0183 dma-coherent;
0184 #iommu-cells = <1>;
0185 msi-parent = <&its 0x10000>;
0186 };
0187
0188 panel {
0189 compatible = "arm,rtsm-display";
0190 port {
0191 panel_in: endpoint {
0192 remote-endpoint = <&clcd_pads>;
0193 };
0194 };
0195 };
0196
0197 bus@8000000 {
0198 #interrupt-cells = <1>;
0199 interrupt-map-mask = <0 0 63>;
0200 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0201 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0202 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0203 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0204 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0205 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0206 <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0207 <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0208 <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0209 <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0210 <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0211 <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0212 <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0213 <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0214 <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0215 <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0216 <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0217 <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0218 <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0219 <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0220 <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0221 <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0222 <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0223 <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0224 <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0225 <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0226 <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0227 <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0228 <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0229 <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0230 <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0231 <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
0232 <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0233 <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0234 <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0235 <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0236 <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0237 <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0238 <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0239 <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0240 <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0241 <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0242 <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0243 <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
0244 <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
0245 <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0246 };
0247 };
