0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * ARM Ltd.
0004 *
0005 * ARMv8 Foundation model DTS
0006 */
0007
0008 /dts-v1/;
0009
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011
0012 /memreserve/ 0x80000000 0x00010000;
0013
0014 / {
0015 model = "Foundation-v8A";
0016 compatible = "arm,foundation-aarch64", "arm,vexpress";
0017 interrupt-parent = <&gic>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 chosen { };
0022
0023 aliases {
0024 serial0 = &v2m_serial0;
0025 serial1 = &v2m_serial1;
0026 serial2 = &v2m_serial2;
0027 serial3 = &v2m_serial3;
0028 };
0029
0030 cpus {
0031 #address-cells = <2>;
0032 #size-cells = <0>;
0033
0034 cpu0: cpu@0 {
0035 device_type = "cpu";
0036 compatible = "arm,armv8";
0037 reg = <0x0 0x0>;
0038 next-level-cache = <&L2_0>;
0039 };
0040 cpu1: cpu@1 {
0041 device_type = "cpu";
0042 compatible = "arm,armv8";
0043 reg = <0x0 0x1>;
0044 next-level-cache = <&L2_0>;
0045 };
0046 cpu2: cpu@2 {
0047 device_type = "cpu";
0048 compatible = "arm,armv8";
0049 reg = <0x0 0x2>;
0050 next-level-cache = <&L2_0>;
0051 };
0052 cpu3: cpu@3 {
0053 device_type = "cpu";
0054 compatible = "arm,armv8";
0055 reg = <0x0 0x3>;
0056 next-level-cache = <&L2_0>;
0057 };
0058
0059 L2_0: l2-cache0 {
0060 compatible = "cache";
0061 };
0062 };
0063
0064 memory@80000000 {
0065 device_type = "memory";
0066 reg = <0x00000000 0x80000000 0 0x80000000>,
0067 <0x00000008 0x80000000 0 0x80000000>;
0068 };
0069
0070 timer {
0071 compatible = "arm,armv8-timer";
0072 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0073 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0074 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0075 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0076 clock-frequency = <100000000>;
0077 };
0078
0079 pmu {
0080 compatible = "arm,armv8-pmuv3";
0081 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
0084 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0085 };
0086
0087 watchdog@2a440000 {
0088 compatible = "arm,sbsa-gwdt";
0089 reg = <0x0 0x2a440000 0 0x1000>,
0090 <0x0 0x2a450000 0 0x1000>;
0091 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0092 timeout-sec = <30>;
0093 };
0094
0095 v2m_clk24mhz: clk24mhz {
0096 compatible = "fixed-clock";
0097 #clock-cells = <0>;
0098 clock-frequency = <24000000>;
0099 clock-output-names = "v2m:clk24mhz";
0100 };
0101
0102 v2m_refclk1mhz: refclk1mhz {
0103 compatible = "fixed-clock";
0104 #clock-cells = <0>;
0105 clock-frequency = <1000000>;
0106 clock-output-names = "v2m:refclk1mhz";
0107 };
0108
0109 v2m_refclk32khz: refclk32khz {
0110 compatible = "fixed-clock";
0111 #clock-cells = <0>;
0112 clock-frequency = <32768>;
0113 clock-output-names = "v2m:refclk32khz";
0114 };
0115
0116 bus@8000000 {
0117 compatible = "arm,vexpress,v2m-p1", "simple-bus";
0118 #address-cells = <2>; /* SMB chipselect number and offset */
0119 #size-cells = <1>;
0120
0121 ranges = <0 0 0 0x08000000 0x04000000>,
0122 <1 0 0 0x14000000 0x04000000>,
0123 <2 0 0 0x18000000 0x04000000>,
0124 <3 0 0 0x1c000000 0x04000000>,
0125 <4 0 0 0x0c000000 0x04000000>,
0126 <5 0 0 0x10000000 0x04000000>;
0127
0128 #interrupt-cells = <1>;
0129 interrupt-map-mask = <0 0 63>;
0130 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0131 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0132 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0133 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0134 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0135 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0136 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0137 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0138 <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0139 <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0140 <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0141 <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0142 <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0143 <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0144 <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0145 <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0146 <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0147 <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0148 <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0149 <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0150 <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0151 <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0152 <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0153 <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0154 <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0155 <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0156 <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0157 <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0158 <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0159 <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0160 <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0161 <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
0162 <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0163 <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0164 <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0165 <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0166 <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0167 <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0168 <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0169 <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0170 <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0171 <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0172 <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0173
0174 ethernet@202000000 {
0175 compatible = "smsc,lan91c111";
0176 reg = <2 0x02000000 0x10000>;
0177 interrupts = <15>;
0178 };
0179
0180 iofpga-bus@300000000 {
0181 compatible = "simple-bus";
0182 #address-cells = <1>;
0183 #size-cells = <1>;
0184 ranges = <0 3 0 0x200000>;
0185
0186 v2m_sysreg: sysreg@10000 {
0187 compatible = "arm,vexpress-sysreg";
0188 reg = <0x010000 0x1000>;
0189 };
0190
0191 v2m_serial0: serial@90000 {
0192 compatible = "arm,pl011", "arm,primecell";
0193 reg = <0x090000 0x1000>;
0194 interrupts = <5>;
0195 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0196 clock-names = "uartclk", "apb_pclk";
0197 };
0198
0199 v2m_serial1: serial@a0000 {
0200 compatible = "arm,pl011", "arm,primecell";
0201 reg = <0x0a0000 0x1000>;
0202 interrupts = <6>;
0203 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0204 clock-names = "uartclk", "apb_pclk";
0205 };
0206
0207 v2m_serial2: serial@b0000 {
0208 compatible = "arm,pl011", "arm,primecell";
0209 reg = <0x0b0000 0x1000>;
0210 interrupts = <7>;
0211 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0212 clock-names = "uartclk", "apb_pclk";
0213 };
0214
0215 v2m_serial3: serial@c0000 {
0216 compatible = "arm,pl011", "arm,primecell";
0217 reg = <0x0c0000 0x1000>;
0218 interrupts = <8>;
0219 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
0220 clock-names = "uartclk", "apb_pclk";
0221 };
0222
0223 virtio@130000 {
0224 compatible = "virtio,mmio";
0225 reg = <0x130000 0x200>;
0226 interrupts = <42>;
0227 };
0228 };
0229 };
0230 };
