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0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
0004 */
0005
0006 #include <dt-bindings/clock/axg-aoclkc.h>
0007 #include <dt-bindings/clock/axg-audio-clkc.h>
0008 #include <dt-bindings/clock/axg-clkc.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/gpio/meson-axg-gpio.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
0014 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
0015 #include <dt-bindings/power/meson-axg-power.h>
0016
0017 / {
0018 compatible = "amlogic,meson-axg";
0019
0020 interrupt-parent = <&gic>;
0021 #address-cells = <2>;
0022 #size-cells = <2>;
0023
0024 tdmif_a: audio-controller-0 {
0025 compatible = "amlogic,axg-tdm-iface";
0026 #sound-dai-cells = <0>;
0027 sound-name-prefix = "TDM_A";
0028 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
0029 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
0030 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
0031 clock-names = "mclk", "sclk", "lrclk";
0032 status = "disabled";
0033 };
0034
0035 tdmif_b: audio-controller-1 {
0036 compatible = "amlogic,axg-tdm-iface";
0037 #sound-dai-cells = <0>;
0038 sound-name-prefix = "TDM_B";
0039 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
0040 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
0041 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
0042 clock-names = "mclk", "sclk", "lrclk";
0043 status = "disabled";
0044 };
0045
0046 tdmif_c: audio-controller-2 {
0047 compatible = "amlogic,axg-tdm-iface";
0048 #sound-dai-cells = <0>;
0049 sound-name-prefix = "TDM_C";
0050 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
0051 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
0052 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
0053 clock-names = "mclk", "sclk", "lrclk";
0054 status = "disabled";
0055 };
0056
0057 arm-pmu {
0058 compatible = "arm,cortex-a53-pmu";
0059 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0060 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0061 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0062 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0063 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0064 };
0065
0066 cpus {
0067 #address-cells = <0x2>;
0068 #size-cells = <0x0>;
0069
0070 cpu0: cpu@0 {
0071 device_type = "cpu";
0072 compatible = "arm,cortex-a53";
0073 reg = <0x0 0x0>;
0074 enable-method = "psci";
0075 next-level-cache = <&l2>;
0076 clocks = <&scpi_dvfs 0>;
0077 };
0078
0079 cpu1: cpu@1 {
0080 device_type = "cpu";
0081 compatible = "arm,cortex-a53";
0082 reg = <0x0 0x1>;
0083 enable-method = "psci";
0084 next-level-cache = <&l2>;
0085 clocks = <&scpi_dvfs 0>;
0086 };
0087
0088 cpu2: cpu@2 {
0089 device_type = "cpu";
0090 compatible = "arm,cortex-a53";
0091 reg = <0x0 0x2>;
0092 enable-method = "psci";
0093 next-level-cache = <&l2>;
0094 clocks = <&scpi_dvfs 0>;
0095 };
0096
0097 cpu3: cpu@3 {
0098 device_type = "cpu";
0099 compatible = "arm,cortex-a53";
0100 reg = <0x0 0x3>;
0101 enable-method = "psci";
0102 next-level-cache = <&l2>;
0103 clocks = <&scpi_dvfs 0>;
0104 };
0105
0106 l2: l2-cache0 {
0107 compatible = "cache";
0108 };
0109 };
0110
0111 sm: secure-monitor {
0112 compatible = "amlogic,meson-gxbb-sm";
0113 };
0114
0115 efuse: efuse {
0116 compatible = "amlogic,meson-gxbb-efuse";
0117 clocks = <&clkc CLKID_EFUSE>;
0118 #address-cells = <1>;
0119 #size-cells = <1>;
0120 read-only;
0121 secure-monitor = <&sm>;
0122 };
0123
0124 psci {
0125 compatible = "arm,psci-1.0";
0126 method = "smc";
0127 };
0128
0129 reserved-memory {
0130 #address-cells = <2>;
0131 #size-cells = <2>;
0132 ranges;
0133
0134 /* 16 MiB reserved for Hardware ROM Firmware */
0135 hwrom_reserved: hwrom@0 {
0136 reg = <0x0 0x0 0x0 0x1000000>;
0137 no-map;
0138 };
0139
0140 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
0141 secmon_reserved: secmon@5000000 {
0142 reg = <0x0 0x05000000 0x0 0x300000>;
0143 no-map;
0144 };
0145 };
0146
0147 scpi {
0148 compatible = "arm,scpi-pre-1.0";
0149 mboxes = <&mailbox 1 &mailbox 2>;
0150 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
0151
0152 scpi_clocks: clocks {
0153 compatible = "arm,scpi-clocks";
0154
0155 scpi_dvfs: clock-controller {
0156 compatible = "arm,scpi-dvfs-clocks";
0157 #clock-cells = <1>;
0158 clock-indices = <0>;
0159 clock-output-names = "vcpu";
0160 };
0161 };
0162
0163 scpi_sensors: sensors {
0164 compatible = "amlogic,meson-gxbb-scpi-sensors";
0165 #thermal-sensor-cells = <1>;
0166 };
0167 };
0168
0169 soc {
0170 compatible = "simple-bus";
0171 #address-cells = <2>;
0172 #size-cells = <2>;
0173 ranges;
0174
0175 pcieA: pcie@f9800000 {
0176 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
0177 reg = <0x0 0xf9800000 0x0 0x400000>,
0178 <0x0 0xff646000 0x0 0x2000>,
0179 <0x0 0xf9f00000 0x0 0x100000>;
0180 reg-names = "elbi", "cfg", "config";
0181 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
0182 #interrupt-cells = <1>;
0183 interrupt-map-mask = <0 0 0 0>;
0184 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
0185 bus-range = <0x0 0xff>;
0186 #address-cells = <3>;
0187 #size-cells = <2>;
0188 device_type = "pci";
0189 ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
0190
0191 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
0192 clock-names = "general", "pclk", "port";
0193 resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
0194 reset-names = "port", "apb";
0195 num-lanes = <1>;
0196 phys = <&pcie_phy>;
0197 phy-names = "pcie";
0198 status = "disabled";
0199 };
0200
0201 pcieB: pcie@fa000000 {
0202 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
0203 reg = <0x0 0xfa000000 0x0 0x400000>,
0204 <0x0 0xff648000 0x0 0x2000>,
0205 <0x0 0xfa400000 0x0 0x100000>;
0206 reg-names = "elbi", "cfg", "config";
0207 interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
0208 #interrupt-cells = <1>;
0209 interrupt-map-mask = <0 0 0 0>;
0210 interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
0211 bus-range = <0x0 0xff>;
0212 #address-cells = <3>;
0213 #size-cells = <2>;
0214 device_type = "pci";
0215 ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
0216
0217 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
0218 clock-names = "general", "pclk", "port";
0219 resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
0220 reset-names = "port", "apb";
0221 num-lanes = <1>;
0222 phys = <&pcie_phy>;
0223 phy-names = "pcie";
0224 status = "disabled";
0225 };
0226
0227 usb: usb@ffe09080 {
0228 compatible = "amlogic,meson-axg-usb-ctrl";
0229 reg = <0x0 0xffe09080 0x0 0x20>;
0230 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0231 #address-cells = <2>;
0232 #size-cells = <2>;
0233 ranges;
0234
0235 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
0236 clock-names = "usb_ctrl", "ddr";
0237 resets = <&reset RESET_USB_OTG>;
0238
0239 dr_mode = "otg";
0240
0241 phys = <&usb2_phy1>;
0242 phy-names = "usb2-phy1";
0243
0244 dwc2: usb@ff400000 {
0245 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
0246 reg = <0x0 0xff400000 0x0 0x40000>;
0247 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0248 clocks = <&clkc CLKID_USB1>;
0249 clock-names = "otg";
0250 phys = <&usb2_phy1>;
0251 dr_mode = "peripheral";
0252 g-rx-fifo-size = <192>;
0253 g-np-tx-fifo-size = <128>;
0254 g-tx-fifo-size = <128 128 16 16 16>;
0255 };
0256
0257 dwc3: usb@ff500000 {
0258 compatible = "snps,dwc3";
0259 reg = <0x0 0xff500000 0x0 0x100000>;
0260 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0261 dr_mode = "host";
0262 maximum-speed = "high-speed";
0263 snps,dis_u2_susphy_quirk;
0264 };
0265 };
0266
0267 ethmac: ethernet@ff3f0000 {
0268 compatible = "amlogic,meson-axg-dwmac",
0269 "snps,dwmac-3.70a",
0270 "snps,dwmac";
0271 reg = <0x0 0xff3f0000 0x0 0x10000>,
0272 <0x0 0xff634540 0x0 0x8>;
0273 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0274 interrupt-names = "macirq";
0275 clocks = <&clkc CLKID_ETH>,
0276 <&clkc CLKID_FCLK_DIV2>,
0277 <&clkc CLKID_MPLL2>,
0278 <&clkc CLKID_FCLK_DIV2>;
0279 clock-names = "stmmaceth", "clkin0", "clkin1",
0280 "timing-adjustment";
0281 rx-fifo-depth = <4096>;
0282 tx-fifo-depth = <2048>;
0283 power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
0284 status = "disabled";
0285 };
0286
0287 pcie_phy: phy@ff644000 {
0288 compatible = "amlogic,axg-pcie-phy";
0289 reg = <0x0 0xff644000 0x0 0x1c>;
0290 resets = <&reset RESET_PCIE_PHY>;
0291 phys = <&mipi_pcie_analog_dphy>;
0292 phy-names = "analog";
0293 #phy-cells = <0>;
0294 };
0295
0296 pdm: audio-controller@ff632000 {
0297 compatible = "amlogic,axg-pdm";
0298 reg = <0x0 0xff632000 0x0 0x34>;
0299 #sound-dai-cells = <0>;
0300 sound-name-prefix = "PDM";
0301 clocks = <&clkc_audio AUD_CLKID_PDM>,
0302 <&clkc_audio AUD_CLKID_PDM_DCLK>,
0303 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
0304 clock-names = "pclk", "dclk", "sysclk";
0305 status = "disabled";
0306 };
0307
0308 periphs: bus@ff634000 {
0309 compatible = "simple-bus";
0310 reg = <0x0 0xff634000 0x0 0x2000>;
0311 #address-cells = <2>;
0312 #size-cells = <2>;
0313 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
0314
0315 hwrng: rng@18 {
0316 compatible = "amlogic,meson-rng";
0317 reg = <0x0 0x18 0x0 0x4>;
0318 clocks = <&clkc CLKID_RNG0>;
0319 clock-names = "core";
0320 };
0321
0322 pinctrl_periphs: pinctrl@480 {
0323 compatible = "amlogic,meson-axg-periphs-pinctrl";
0324 #address-cells = <2>;
0325 #size-cells = <2>;
0326 ranges;
0327
0328 gpio: bank@480 {
0329 reg = <0x0 0x00480 0x0 0x40>,
0330 <0x0 0x004e8 0x0 0x14>,
0331 <0x0 0x00520 0x0 0x14>,
0332 <0x0 0x00430 0x0 0x3c>;
0333 reg-names = "mux", "pull", "pull-enable", "gpio";
0334 gpio-controller;
0335 #gpio-cells = <2>;
0336 gpio-ranges = <&pinctrl_periphs 0 0 86>;
0337 };
0338
0339 i2c0_pins: i2c0 {
0340 mux {
0341 groups = "i2c0_sck",
0342 "i2c0_sda";
0343 function = "i2c0";
0344 bias-disable;
0345 };
0346 };
0347
0348 i2c1_x_pins: i2c1_x {
0349 mux {
0350 groups = "i2c1_sck_x",
0351 "i2c1_sda_x";
0352 function = "i2c1";
0353 bias-disable;
0354 };
0355 };
0356
0357 i2c1_z_pins: i2c1_z {
0358 mux {
0359 groups = "i2c1_sck_z",
0360 "i2c1_sda_z";
0361 function = "i2c1";
0362 bias-disable;
0363 };
0364 };
0365
0366 i2c2_a_pins: i2c2_a {
0367 mux {
0368 groups = "i2c2_sck_a",
0369 "i2c2_sda_a";
0370 function = "i2c2";
0371 bias-disable;
0372 };
0373 };
0374
0375 i2c2_x_pins: i2c2_x {
0376 mux {
0377 groups = "i2c2_sck_x",
0378 "i2c2_sda_x";
0379 function = "i2c2";
0380 bias-disable;
0381 };
0382 };
0383
0384 i2c3_a6_pins: i2c3_a6 {
0385 mux {
0386 groups = "i2c3_sda_a6",
0387 "i2c3_sck_a7";
0388 function = "i2c3";
0389 bias-disable;
0390 };
0391 };
0392
0393 i2c3_a12_pins: i2c3_a12 {
0394 mux {
0395 groups = "i2c3_sda_a12",
0396 "i2c3_sck_a13";
0397 function = "i2c3";
0398 bias-disable;
0399 };
0400 };
0401
0402 i2c3_a19_pins: i2c3_a19 {
0403 mux {
0404 groups = "i2c3_sda_a19",
0405 "i2c3_sck_a20";
0406 function = "i2c3";
0407 bias-disable;
0408 };
0409 };
0410
0411 emmc_pins: emmc {
0412 mux-0 {
0413 groups = "emmc_nand_d0",
0414 "emmc_nand_d1",
0415 "emmc_nand_d2",
0416 "emmc_nand_d3",
0417 "emmc_nand_d4",
0418 "emmc_nand_d5",
0419 "emmc_nand_d6",
0420 "emmc_nand_d7",
0421 "emmc_cmd";
0422 function = "emmc";
0423 bias-pull-up;
0424 };
0425
0426 mux-1 {
0427 groups = "emmc_clk";
0428 function = "emmc";
0429 bias-disable;
0430 };
0431 };
0432
0433 emmc_ds_pins: emmc_ds {
0434 mux {
0435 groups = "emmc_ds";
0436 function = "emmc";
0437 bias-pull-down;
0438 };
0439 };
0440
0441 emmc_clk_gate_pins: emmc_clk_gate {
0442 mux {
0443 groups = "BOOT_8";
0444 function = "gpio_periphs";
0445 bias-pull-down;
0446 };
0447 };
0448
0449 eth_rgmii_x_pins: eth-x-rgmii {
0450 mux {
0451 groups = "eth_mdio_x",
0452 "eth_mdc_x",
0453 "eth_rgmii_rx_clk_x",
0454 "eth_rx_dv_x",
0455 "eth_rxd0_x",
0456 "eth_rxd1_x",
0457 "eth_rxd2_rgmii",
0458 "eth_rxd3_rgmii",
0459 "eth_rgmii_tx_clk",
0460 "eth_txen_x",
0461 "eth_txd0_x",
0462 "eth_txd1_x",
0463 "eth_txd2_rgmii",
0464 "eth_txd3_rgmii";
0465 function = "eth";
0466 bias-disable;
0467 };
0468 };
0469
0470 eth_rgmii_y_pins: eth-y-rgmii {
0471 mux {
0472 groups = "eth_mdio_y",
0473 "eth_mdc_y",
0474 "eth_rgmii_rx_clk_y",
0475 "eth_rx_dv_y",
0476 "eth_rxd0_y",
0477 "eth_rxd1_y",
0478 "eth_rxd2_rgmii",
0479 "eth_rxd3_rgmii",
0480 "eth_rgmii_tx_clk",
0481 "eth_txen_y",
0482 "eth_txd0_y",
0483 "eth_txd1_y",
0484 "eth_txd2_rgmii",
0485 "eth_txd3_rgmii";
0486 function = "eth";
0487 bias-disable;
0488 };
0489 };
0490
0491 eth_rmii_x_pins: eth-x-rmii {
0492 mux {
0493 groups = "eth_mdio_x",
0494 "eth_mdc_x",
0495 "eth_rgmii_rx_clk_x",
0496 "eth_rx_dv_x",
0497 "eth_rxd0_x",
0498 "eth_rxd1_x",
0499 "eth_txen_x",
0500 "eth_txd0_x",
0501 "eth_txd1_x";
0502 function = "eth";
0503 bias-disable;
0504 };
0505 };
0506
0507 eth_rmii_y_pins: eth-y-rmii {
0508 mux {
0509 groups = "eth_mdio_y",
0510 "eth_mdc_y",
0511 "eth_rgmii_rx_clk_y",
0512 "eth_rx_dv_y",
0513 "eth_rxd0_y",
0514 "eth_rxd1_y",
0515 "eth_txen_y",
0516 "eth_txd0_y",
0517 "eth_txd1_y";
0518 function = "eth";
0519 bias-disable;
0520 };
0521 };
0522
0523 mclk_b_pins: mclk_b {
0524 mux {
0525 groups = "mclk_b";
0526 function = "mclk_b";
0527 bias-disable;
0528 };
0529 };
0530
0531 mclk_c_pins: mclk_c {
0532 mux {
0533 groups = "mclk_c";
0534 function = "mclk_c";
0535 bias-disable;
0536 };
0537 };
0538
0539 pdm_dclk_a14_pins: pdm_dclk_a14 {
0540 mux {
0541 groups = "pdm_dclk_a14";
0542 function = "pdm";
0543 bias-disable;
0544 };
0545 };
0546
0547 pdm_dclk_a19_pins: pdm_dclk_a19 {
0548 mux {
0549 groups = "pdm_dclk_a19";
0550 function = "pdm";
0551 bias-disable;
0552 };
0553 };
0554
0555 pdm_din0_pins: pdm_din0 {
0556 mux {
0557 groups = "pdm_din0";
0558 function = "pdm";
0559 bias-disable;
0560 };
0561 };
0562
0563 pdm_din1_pins: pdm_din1 {
0564 mux {
0565 groups = "pdm_din1";
0566 function = "pdm";
0567 bias-disable;
0568 };
0569 };
0570
0571 pdm_din2_pins: pdm_din2 {
0572 mux {
0573 groups = "pdm_din2";
0574 function = "pdm";
0575 bias-disable;
0576 };
0577 };
0578
0579 pdm_din3_pins: pdm_din3 {
0580 mux {
0581 groups = "pdm_din3";
0582 function = "pdm";
0583 bias-disable;
0584 };
0585 };
0586
0587 pwm_a_a_pins: pwm_a_a {
0588 mux {
0589 groups = "pwm_a_a";
0590 function = "pwm_a";
0591 bias-disable;
0592 };
0593 };
0594
0595 pwm_a_x18_pins: pwm_a_x18 {
0596 mux {
0597 groups = "pwm_a_x18";
0598 function = "pwm_a";
0599 bias-disable;
0600 };
0601 };
0602
0603 pwm_a_x20_pins: pwm_a_x20 {
0604 mux {
0605 groups = "pwm_a_x20";
0606 function = "pwm_a";
0607 bias-disable;
0608 };
0609 };
0610
0611 pwm_a_z_pins: pwm_a_z {
0612 mux {
0613 groups = "pwm_a_z";
0614 function = "pwm_a";
0615 bias-disable;
0616 };
0617 };
0618
0619 pwm_b_a_pins: pwm_b_a {
0620 mux {
0621 groups = "pwm_b_a";
0622 function = "pwm_b";
0623 bias-disable;
0624 };
0625 };
0626
0627 pwm_b_x_pins: pwm_b_x {
0628 mux {
0629 groups = "pwm_b_x";
0630 function = "pwm_b";
0631 bias-disable;
0632 };
0633 };
0634
0635 pwm_b_z_pins: pwm_b_z {
0636 mux {
0637 groups = "pwm_b_z";
0638 function = "pwm_b";
0639 bias-disable;
0640 };
0641 };
0642
0643 pwm_c_a_pins: pwm_c_a {
0644 mux {
0645 groups = "pwm_c_a";
0646 function = "pwm_c";
0647 bias-disable;
0648 };
0649 };
0650
0651 pwm_c_x10_pins: pwm_c_x10 {
0652 mux {
0653 groups = "pwm_c_x10";
0654 function = "pwm_c";
0655 bias-disable;
0656 };
0657 };
0658
0659 pwm_c_x17_pins: pwm_c_x17 {
0660 mux {
0661 groups = "pwm_c_x17";
0662 function = "pwm_c";
0663 bias-disable;
0664 };
0665 };
0666
0667 pwm_d_x11_pins: pwm_d_x11 {
0668 mux {
0669 groups = "pwm_d_x11";
0670 function = "pwm_d";
0671 bias-disable;
0672 };
0673 };
0674
0675 pwm_d_x16_pins: pwm_d_x16 {
0676 mux {
0677 groups = "pwm_d_x16";
0678 function = "pwm_d";
0679 bias-disable;
0680 };
0681 };
0682
0683 sdio_pins: sdio {
0684 mux-0 {
0685 groups = "sdio_d0",
0686 "sdio_d1",
0687 "sdio_d2",
0688 "sdio_d3",
0689 "sdio_cmd";
0690 function = "sdio";
0691 bias-pull-up;
0692 };
0693
0694 mux-1 {
0695 groups = "sdio_clk";
0696 function = "sdio";
0697 bias-disable;
0698 };
0699 };
0700
0701 sdio_clk_gate_pins: sdio_clk_gate {
0702 mux {
0703 groups = "GPIOX_4";
0704 function = "gpio_periphs";
0705 bias-pull-down;
0706 };
0707 };
0708
0709 spdif_in_z_pins: spdif_in_z {
0710 mux {
0711 groups = "spdif_in_z";
0712 function = "spdif_in";
0713 bias-disable;
0714 };
0715 };
0716
0717 spdif_in_a1_pins: spdif_in_a1 {
0718 mux {
0719 groups = "spdif_in_a1";
0720 function = "spdif_in";
0721 bias-disable;
0722 };
0723 };
0724
0725 spdif_in_a7_pins: spdif_in_a7 {
0726 mux {
0727 groups = "spdif_in_a7";
0728 function = "spdif_in";
0729 bias-disable;
0730 };
0731 };
0732
0733 spdif_in_a19_pins: spdif_in_a19 {
0734 mux {
0735 groups = "spdif_in_a19";
0736 function = "spdif_in";
0737 bias-disable;
0738 };
0739 };
0740
0741 spdif_in_a20_pins: spdif_in_a20 {
0742 mux {
0743 groups = "spdif_in_a20";
0744 function = "spdif_in";
0745 bias-disable;
0746 };
0747 };
0748
0749 spdif_out_a1_pins: spdif_out_a1 {
0750 mux {
0751 groups = "spdif_out_a1";
0752 function = "spdif_out";
0753 bias-disable;
0754 };
0755 };
0756
0757 spdif_out_a11_pins: spdif_out_a11 {
0758 mux {
0759 groups = "spdif_out_a11";
0760 function = "spdif_out";
0761 bias-disable;
0762 };
0763 };
0764
0765 spdif_out_a19_pins: spdif_out_a19 {
0766 mux {
0767 groups = "spdif_out_a19";
0768 function = "spdif_out";
0769 bias-disable;
0770 };
0771 };
0772
0773 spdif_out_a20_pins: spdif_out_a20 {
0774 mux {
0775 groups = "spdif_out_a20";
0776 function = "spdif_out";
0777 bias-disable;
0778 };
0779 };
0780
0781 spdif_out_z_pins: spdif_out_z {
0782 mux {
0783 groups = "spdif_out_z";
0784 function = "spdif_out";
0785 bias-disable;
0786 };
0787 };
0788
0789 spi0_pins: spi0 {
0790 mux {
0791 groups = "spi0_miso",
0792 "spi0_mosi",
0793 "spi0_clk";
0794 function = "spi0";
0795 bias-disable;
0796 };
0797 };
0798
0799 spi0_ss0_pins: spi0_ss0 {
0800 mux {
0801 groups = "spi0_ss0";
0802 function = "spi0";
0803 bias-disable;
0804 };
0805 };
0806
0807 spi0_ss1_pins: spi0_ss1 {
0808 mux {
0809 groups = "spi0_ss1";
0810 function = "spi0";
0811 bias-disable;
0812 };
0813 };
0814
0815 spi0_ss2_pins: spi0_ss2 {
0816 mux {
0817 groups = "spi0_ss2";
0818 function = "spi0";
0819 bias-disable;
0820 };
0821 };
0822
0823 spi1_a_pins: spi1_a {
0824 mux {
0825 groups = "spi1_miso_a",
0826 "spi1_mosi_a",
0827 "spi1_clk_a";
0828 function = "spi1";
0829 bias-disable;
0830 };
0831 };
0832
0833 spi1_ss0_a_pins: spi1_ss0_a {
0834 mux {
0835 groups = "spi1_ss0_a";
0836 function = "spi1";
0837 bias-disable;
0838 };
0839 };
0840
0841 spi1_ss1_pins: spi1_ss1 {
0842 mux {
0843 groups = "spi1_ss1";
0844 function = "spi1";
0845 bias-disable;
0846 };
0847 };
0848
0849 spi1_x_pins: spi1_x {
0850 mux {
0851 groups = "spi1_miso_x",
0852 "spi1_mosi_x",
0853 "spi1_clk_x";
0854 function = "spi1";
0855 bias-disable;
0856 };
0857 };
0858
0859 spi1_ss0_x_pins: spi1_ss0_x {
0860 mux {
0861 groups = "spi1_ss0_x";
0862 function = "spi1";
0863 bias-disable;
0864 };
0865 };
0866
0867 tdma_din0_pins: tdma_din0 {
0868 mux {
0869 groups = "tdma_din0";
0870 function = "tdma";
0871 bias-disable;
0872 };
0873 };
0874
0875 tdma_dout0_x14_pins: tdma_dout0_x14 {
0876 mux {
0877 groups = "tdma_dout0_x14";
0878 function = "tdma";
0879 bias-disable;
0880 };
0881 };
0882
0883 tdma_dout0_x15_pins: tdma_dout0_x15 {
0884 mux {
0885 groups = "tdma_dout0_x15";
0886 function = "tdma";
0887 bias-disable;
0888 };
0889 };
0890
0891 tdma_dout1_pins: tdma_dout1 {
0892 mux {
0893 groups = "tdma_dout1";
0894 function = "tdma";
0895 bias-disable;
0896 };
0897 };
0898
0899 tdma_din1_pins: tdma_din1 {
0900 mux {
0901 groups = "tdma_din1";
0902 function = "tdma";
0903 bias-disable;
0904 };
0905 };
0906
0907 tdma_fs_pins: tdma_fs {
0908 mux {
0909 groups = "tdma_fs";
0910 function = "tdma";
0911 bias-disable;
0912 };
0913 };
0914
0915 tdma_fs_slv_pins: tdma_fs_slv {
0916 mux {
0917 groups = "tdma_fs_slv";
0918 function = "tdma";
0919 bias-disable;
0920 };
0921 };
0922
0923 tdma_sclk_pins: tdma_sclk {
0924 mux {
0925 groups = "tdma_sclk";
0926 function = "tdma";
0927 bias-disable;
0928 };
0929 };
0930
0931 tdma_sclk_slv_pins: tdma_sclk_slv {
0932 mux {
0933 groups = "tdma_sclk_slv";
0934 function = "tdma";
0935 bias-disable;
0936 };
0937 };
0938
0939 tdmb_din0_pins: tdmb_din0 {
0940 mux {
0941 groups = "tdmb_din0";
0942 function = "tdmb";
0943 bias-disable;
0944 };
0945 };
0946
0947 tdmb_din1_pins: tdmb_din1 {
0948 mux {
0949 groups = "tdmb_din1";
0950 function = "tdmb";
0951 bias-disable;
0952 };
0953 };
0954
0955 tdmb_din2_pins: tdmb_din2 {
0956 mux {
0957 groups = "tdmb_din2";
0958 function = "tdmb";
0959 bias-disable;
0960 };
0961 };
0962
0963 tdmb_din3_pins: tdmb_din3 {
0964 mux {
0965 groups = "tdmb_din3";
0966 function = "tdmb";
0967 bias-disable;
0968 };
0969 };
0970
0971 tdmb_dout0_pins: tdmb_dout0 {
0972 mux {
0973 groups = "tdmb_dout0";
0974 function = "tdmb";
0975 bias-disable;
0976 };
0977 };
0978
0979 tdmb_dout1_pins: tdmb_dout1 {
0980 mux {
0981 groups = "tdmb_dout1";
0982 function = "tdmb";
0983 bias-disable;
0984 };
0985 };
0986
0987 tdmb_dout2_pins: tdmb_dout2 {
0988 mux {
0989 groups = "tdmb_dout2";
0990 function = "tdmb";
0991 bias-disable;
0992 };
0993 };
0994
0995 tdmb_dout3_pins: tdmb_dout3 {
0996 mux {
0997 groups = "tdmb_dout3";
0998 function = "tdmb";
0999 bias-disable;
1000 };
1001 };
1002
1003 tdmb_fs_pins: tdmb_fs {
1004 mux {
1005 groups = "tdmb_fs";
1006 function = "tdmb";
1007 bias-disable;
1008 };
1009 };
1010
1011 tdmb_fs_slv_pins: tdmb_fs_slv {
1012 mux {
1013 groups = "tdmb_fs_slv";
1014 function = "tdmb";
1015 bias-disable;
1016 };
1017 };
1018
1019 tdmb_sclk_pins: tdmb_sclk {
1020 mux {
1021 groups = "tdmb_sclk";
1022 function = "tdmb";
1023 bias-disable;
1024 };
1025 };
1026
1027 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1028 mux {
1029 groups = "tdmb_sclk_slv";
1030 function = "tdmb";
1031 bias-disable;
1032 };
1033 };
1034
1035 tdmc_fs_pins: tdmc_fs {
1036 mux {
1037 groups = "tdmc_fs";
1038 function = "tdmc";
1039 bias-disable;
1040 };
1041 };
1042
1043 tdmc_fs_slv_pins: tdmc_fs_slv {
1044 mux {
1045 groups = "tdmc_fs_slv";
1046 function = "tdmc";
1047 bias-disable;
1048 };
1049 };
1050
1051 tdmc_sclk_pins: tdmc_sclk {
1052 mux {
1053 groups = "tdmc_sclk";
1054 function = "tdmc";
1055 bias-disable;
1056 };
1057 };
1058
1059 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1060 mux {
1061 groups = "tdmc_sclk_slv";
1062 function = "tdmc";
1063 bias-disable;
1064 };
1065 };
1066
1067 tdmc_din0_pins: tdmc_din0 {
1068 mux {
1069 groups = "tdmc_din0";
1070 function = "tdmc";
1071 bias-disable;
1072 };
1073 };
1074
1075 tdmc_din1_pins: tdmc_din1 {
1076 mux {
1077 groups = "tdmc_din1";
1078 function = "tdmc";
1079 bias-disable;
1080 };
1081 };
1082
1083 tdmc_din2_pins: tdmc_din2 {
1084 mux {
1085 groups = "tdmc_din2";
1086 function = "tdmc";
1087 bias-disable;
1088 };
1089 };
1090
1091 tdmc_din3_pins: tdmc_din3 {
1092 mux {
1093 groups = "tdmc_din3";
1094 function = "tdmc";
1095 bias-disable;
1096 };
1097 };
1098
1099 tdmc_dout0_pins: tdmc_dout0 {
1100 mux {
1101 groups = "tdmc_dout0";
1102 function = "tdmc";
1103 bias-disable;
1104 };
1105 };
1106
1107 tdmc_dout1_pins: tdmc_dout1 {
1108 mux {
1109 groups = "tdmc_dout1";
1110 function = "tdmc";
1111 bias-disable;
1112 };
1113 };
1114
1115 tdmc_dout2_pins: tdmc_dout2 {
1116 mux {
1117 groups = "tdmc_dout2";
1118 function = "tdmc";
1119 bias-disable;
1120 };
1121 };
1122
1123 tdmc_dout3_pins: tdmc_dout3 {
1124 mux {
1125 groups = "tdmc_dout3";
1126 function = "tdmc";
1127 bias-disable;
1128 };
1129 };
1130
1131 uart_a_pins: uart_a {
1132 mux {
1133 groups = "uart_tx_a",
1134 "uart_rx_a";
1135 function = "uart_a";
1136 bias-disable;
1137 };
1138 };
1139
1140 uart_a_cts_rts_pins: uart_a_cts_rts {
1141 mux {
1142 groups = "uart_cts_a",
1143 "uart_rts_a";
1144 function = "uart_a";
1145 bias-disable;
1146 };
1147 };
1148
1149 uart_b_x_pins: uart_b_x {
1150 mux {
1151 groups = "uart_tx_b_x",
1152 "uart_rx_b_x";
1153 function = "uart_b";
1154 bias-disable;
1155 };
1156 };
1157
1158 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1159 mux {
1160 groups = "uart_cts_b_x",
1161 "uart_rts_b_x";
1162 function = "uart_b";
1163 bias-disable;
1164 };
1165 };
1166
1167 uart_b_z_pins: uart_b_z {
1168 mux {
1169 groups = "uart_tx_b_z",
1170 "uart_rx_b_z";
1171 function = "uart_b";
1172 bias-disable;
1173 };
1174 };
1175
1176 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1177 mux {
1178 groups = "uart_cts_b_z",
1179 "uart_rts_b_z";
1180 function = "uart_b";
1181 bias-disable;
1182 };
1183 };
1184
1185 uart_ao_b_z_pins: uart_ao_b_z {
1186 mux {
1187 groups = "uart_ao_tx_b_z",
1188 "uart_ao_rx_b_z";
1189 function = "uart_ao_b_z";
1190 bias-disable;
1191 };
1192 };
1193
1194 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1195 mux {
1196 groups = "uart_ao_cts_b_z",
1197 "uart_ao_rts_b_z";
1198 function = "uart_ao_b_z";
1199 bias-disable;
1200 };
1201 };
1202 };
1203 };
1204
1205 hiubus: bus@ff63c000 {
1206 compatible = "simple-bus";
1207 reg = <0x0 0xff63c000 0x0 0x1c00>;
1208 #address-cells = <2>;
1209 #size-cells = <2>;
1210 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1211
1212 sysctrl: system-controller@0 {
1213 compatible = "amlogic,meson-axg-hhi-sysctrl",
1214 "simple-mfd", "syscon";
1215 reg = <0 0 0 0x400>;
1216
1217 clkc: clock-controller {
1218 compatible = "amlogic,axg-clkc";
1219 #clock-cells = <1>;
1220 clocks = <&xtal>;
1221 clock-names = "xtal";
1222 };
1223
1224 pwrc: power-controller {
1225 compatible = "amlogic,meson-axg-pwrc";
1226 #power-domain-cells = <1>;
1227 amlogic,ao-sysctrl = <&sysctrl_AO>;
1228 resets = <&reset RESET_VIU>,
1229 <&reset RESET_VENC>,
1230 <&reset RESET_VCBUS>,
1231 <&reset RESET_VENCL>,
1232 <&reset RESET_VID_LOCK>;
1233 reset-names = "viu", "venc", "vcbus",
1234 "vencl", "vid_lock";
1235 clocks = <&clkc CLKID_VPU>,
1236 <&clkc CLKID_VAPB>;
1237 clock-names = "vpu", "vapb";
1238 /*
1239 * VPU clocking is provided by two identical clock paths
1240 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1241 * free mux to safely change frequency while running.
1242 * Same for VAPB but with a final gate after the glitch free mux.
1243 */
1244 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1245 <&clkc CLKID_VPU_0>,
1246 <&clkc CLKID_VPU>, /* Glitch free mux */
1247 <&clkc CLKID_VAPB_0_SEL>,
1248 <&clkc CLKID_VAPB_0>,
1249 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1250 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1251 <0>, /* Do Nothing */
1252 <&clkc CLKID_VPU_0>,
1253 <&clkc CLKID_FCLK_DIV4>,
1254 <0>, /* Do Nothing */
1255 <&clkc CLKID_VAPB_0>;
1256 assigned-clock-rates = <0>, /* Do Nothing */
1257 <250000000>,
1258 <0>, /* Do Nothing */
1259 <0>, /* Do Nothing */
1260 <250000000>,
1261 <0>; /* Do Nothing */
1262 };
1263
1264 mipi_pcie_analog_dphy: phy {
1265 compatible = "amlogic,axg-mipi-pcie-analog-phy";
1266 #phy-cells = <0>;
1267 status = "disabled";
1268 };
1269 };
1270 };
1271
1272 mailbox: mailbox@ff63c404 {
1273 compatible = "amlogic,meson-gxbb-mhu";
1274 reg = <0 0xff63c404 0 0x4c>;
1275 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1276 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1277 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1278 #mbox-cells = <1>;
1279 };
1280
1281 mipi_dphy: phy@ff640000 {
1282 compatible = "amlogic,axg-mipi-dphy";
1283 reg = <0x0 0xff640000 0x0 0x100>;
1284 clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1285 clock-names = "pclk";
1286 resets = <&reset RESET_MIPI_PHY>;
1287 reset-names = "phy";
1288 phys = <&mipi_pcie_analog_dphy>;
1289 phy-names = "analog";
1290 #phy-cells = <0>;
1291 status = "disabled";
1292 };
1293
1294 audio: bus@ff642000 {
1295 compatible = "simple-bus";
1296 reg = <0x0 0xff642000 0x0 0x2000>;
1297 #address-cells = <2>;
1298 #size-cells = <2>;
1299 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1300
1301 clkc_audio: clock-controller@0 {
1302 compatible = "amlogic,axg-audio-clkc";
1303 reg = <0x0 0x0 0x0 0xb4>;
1304 #clock-cells = <1>;
1305
1306 clocks = <&clkc CLKID_AUDIO>,
1307 <&clkc CLKID_MPLL0>,
1308 <&clkc CLKID_MPLL1>,
1309 <&clkc CLKID_MPLL2>,
1310 <&clkc CLKID_MPLL3>,
1311 <&clkc CLKID_HIFI_PLL>,
1312 <&clkc CLKID_FCLK_DIV3>,
1313 <&clkc CLKID_FCLK_DIV4>,
1314 <&clkc CLKID_GP0_PLL>;
1315 clock-names = "pclk",
1316 "mst_in0",
1317 "mst_in1",
1318 "mst_in2",
1319 "mst_in3",
1320 "mst_in4",
1321 "mst_in5",
1322 "mst_in6",
1323 "mst_in7";
1324
1325 resets = <&reset RESET_AUDIO>;
1326 };
1327
1328 toddr_a: audio-controller@100 {
1329 compatible = "amlogic,axg-toddr";
1330 reg = <0x0 0x100 0x0 0x2c>;
1331 #sound-dai-cells = <0>;
1332 sound-name-prefix = "TODDR_A";
1333 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1334 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1335 resets = <&arb AXG_ARB_TODDR_A>;
1336 amlogic,fifo-depth = <512>;
1337 status = "disabled";
1338 };
1339
1340 toddr_b: audio-controller@140 {
1341 compatible = "amlogic,axg-toddr";
1342 reg = <0x0 0x140 0x0 0x2c>;
1343 #sound-dai-cells = <0>;
1344 sound-name-prefix = "TODDR_B";
1345 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1346 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1347 resets = <&arb AXG_ARB_TODDR_B>;
1348 amlogic,fifo-depth = <256>;
1349 status = "disabled";
1350 };
1351
1352 toddr_c: audio-controller@180 {
1353 compatible = "amlogic,axg-toddr";
1354 reg = <0x0 0x180 0x0 0x2c>;
1355 #sound-dai-cells = <0>;
1356 sound-name-prefix = "TODDR_C";
1357 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1358 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1359 resets = <&arb AXG_ARB_TODDR_C>;
1360 amlogic,fifo-depth = <256>;
1361 status = "disabled";
1362 };
1363
1364 frddr_a: audio-controller@1c0 {
1365 compatible = "amlogic,axg-frddr";
1366 reg = <0x0 0x1c0 0x0 0x2c>;
1367 #sound-dai-cells = <0>;
1368 sound-name-prefix = "FRDDR_A";
1369 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1370 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1371 resets = <&arb AXG_ARB_FRDDR_A>;
1372 amlogic,fifo-depth = <512>;
1373 status = "disabled";
1374 };
1375
1376 frddr_b: audio-controller@200 {
1377 compatible = "amlogic,axg-frddr";
1378 reg = <0x0 0x200 0x0 0x2c>;
1379 #sound-dai-cells = <0>;
1380 sound-name-prefix = "FRDDR_B";
1381 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1382 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1383 resets = <&arb AXG_ARB_FRDDR_B>;
1384 amlogic,fifo-depth = <256>;
1385 status = "disabled";
1386 };
1387
1388 frddr_c: audio-controller@240 {
1389 compatible = "amlogic,axg-frddr";
1390 reg = <0x0 0x240 0x0 0x2c>;
1391 #sound-dai-cells = <0>;
1392 sound-name-prefix = "FRDDR_C";
1393 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1394 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1395 resets = <&arb AXG_ARB_FRDDR_C>;
1396 amlogic,fifo-depth = <256>;
1397 status = "disabled";
1398 };
1399
1400 arb: reset-controller@280 {
1401 compatible = "amlogic,meson-axg-audio-arb";
1402 reg = <0x0 0x280 0x0 0x4>;
1403 #reset-cells = <1>;
1404 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1405 };
1406
1407 tdmin_a: audio-controller@300 {
1408 compatible = "amlogic,axg-tdmin";
1409 reg = <0x0 0x300 0x0 0x40>;
1410 sound-name-prefix = "TDMIN_A";
1411 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1412 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1413 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1414 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1415 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1416 clock-names = "pclk", "sclk", "sclk_sel",
1417 "lrclk", "lrclk_sel";
1418 status = "disabled";
1419 };
1420
1421 tdmin_b: audio-controller@340 {
1422 compatible = "amlogic,axg-tdmin";
1423 reg = <0x0 0x340 0x0 0x40>;
1424 sound-name-prefix = "TDMIN_B";
1425 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1426 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1427 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1428 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1429 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1430 clock-names = "pclk", "sclk", "sclk_sel",
1431 "lrclk", "lrclk_sel";
1432 status = "disabled";
1433 };
1434
1435 tdmin_c: audio-controller@380 {
1436 compatible = "amlogic,axg-tdmin";
1437 reg = <0x0 0x380 0x0 0x40>;
1438 sound-name-prefix = "TDMIN_C";
1439 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1440 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1441 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1442 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1443 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1444 clock-names = "pclk", "sclk", "sclk_sel",
1445 "lrclk", "lrclk_sel";
1446 status = "disabled";
1447 };
1448
1449 tdmin_lb: audio-controller@3c0 {
1450 compatible = "amlogic,axg-tdmin";
1451 reg = <0x0 0x3c0 0x0 0x40>;
1452 sound-name-prefix = "TDMIN_LB";
1453 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1454 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1455 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1456 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1457 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1458 clock-names = "pclk", "sclk", "sclk_sel",
1459 "lrclk", "lrclk_sel";
1460 status = "disabled";
1461 };
1462
1463 spdifin: audio-controller@400 {
1464 compatible = "amlogic,axg-spdifin";
1465 reg = <0x0 0x400 0x0 0x30>;
1466 #sound-dai-cells = <0>;
1467 sound-name-prefix = "SPDIFIN";
1468 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1469 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1470 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1471 clock-names = "pclk", "refclk";
1472 status = "disabled";
1473 };
1474
1475 spdifout: audio-controller@480 {
1476 compatible = "amlogic,axg-spdifout";
1477 reg = <0x0 0x480 0x0 0x50>;
1478 #sound-dai-cells = <0>;
1479 sound-name-prefix = "SPDIFOUT";
1480 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1481 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1482 clock-names = "pclk", "mclk";
1483 status = "disabled";
1484 };
1485
1486 tdmout_a: audio-controller@500 {
1487 compatible = "amlogic,axg-tdmout";
1488 reg = <0x0 0x500 0x0 0x40>;
1489 sound-name-prefix = "TDMOUT_A";
1490 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1491 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1492 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1493 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1494 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1495 clock-names = "pclk", "sclk", "sclk_sel",
1496 "lrclk", "lrclk_sel";
1497 status = "disabled";
1498 };
1499
1500 tdmout_b: audio-controller@540 {
1501 compatible = "amlogic,axg-tdmout";
1502 reg = <0x0 0x540 0x0 0x40>;
1503 sound-name-prefix = "TDMOUT_B";
1504 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1505 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1506 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1507 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1508 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1509 clock-names = "pclk", "sclk", "sclk_sel",
1510 "lrclk", "lrclk_sel";
1511 status = "disabled";
1512 };
1513
1514 tdmout_c: audio-controller@580 {
1515 compatible = "amlogic,axg-tdmout";
1516 reg = <0x0 0x580 0x0 0x40>;
1517 sound-name-prefix = "TDMOUT_C";
1518 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1519 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1520 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1521 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1522 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1523 clock-names = "pclk", "sclk", "sclk_sel",
1524 "lrclk", "lrclk_sel";
1525 status = "disabled";
1526 };
1527 };
1528
1529 aobus: bus@ff800000 {
1530 compatible = "simple-bus";
1531 reg = <0x0 0xff800000 0x0 0x100000>;
1532 #address-cells = <2>;
1533 #size-cells = <2>;
1534 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1535
1536 sysctrl_AO: sys-ctrl@0 {
1537 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1538 reg = <0x0 0x0 0x0 0x100>;
1539
1540 clkc_AO: clock-controller {
1541 compatible = "amlogic,meson-axg-aoclkc";
1542 #clock-cells = <1>;
1543 #reset-cells = <1>;
1544 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1545 clock-names = "xtal", "mpeg-clk";
1546 };
1547 };
1548
1549 pinctrl_aobus: pinctrl@14 {
1550 compatible = "amlogic,meson-axg-aobus-pinctrl";
1551 #address-cells = <2>;
1552 #size-cells = <2>;
1553 ranges;
1554
1555 gpio_ao: bank@14 {
1556 reg = <0x0 0x00014 0x0 0x8>,
1557 <0x0 0x0002c 0x0 0x4>,
1558 <0x0 0x00024 0x0 0x8>;
1559 reg-names = "mux", "pull", "gpio";
1560 gpio-controller;
1561 #gpio-cells = <2>;
1562 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1563 };
1564
1565 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1566 mux {
1567 groups = "i2c_ao_sck_4";
1568 function = "i2c_ao";
1569 bias-disable;
1570 };
1571 };
1572
1573 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1574 mux {
1575 groups = "i2c_ao_sck_8";
1576 function = "i2c_ao";
1577 bias-disable;
1578 };
1579 };
1580
1581 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1582 mux {
1583 groups = "i2c_ao_sck_10";
1584 function = "i2c_ao";
1585 bias-disable;
1586 };
1587 };
1588
1589 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1590 mux {
1591 groups = "i2c_ao_sda_5";
1592 function = "i2c_ao";
1593 bias-disable;
1594 };
1595 };
1596
1597 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1598 mux {
1599 groups = "i2c_ao_sda_9";
1600 function = "i2c_ao";
1601 bias-disable;
1602 };
1603 };
1604
1605 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1606 mux {
1607 groups = "i2c_ao_sda_11";
1608 function = "i2c_ao";
1609 bias-disable;
1610 };
1611 };
1612
1613 remote_input_ao_pins: remote_input_ao {
1614 mux {
1615 groups = "remote_input_ao";
1616 function = "remote_input_ao";
1617 bias-disable;
1618 };
1619 };
1620
1621 uart_ao_a_pins: uart_ao_a {
1622 mux {
1623 groups = "uart_ao_tx_a",
1624 "uart_ao_rx_a";
1625 function = "uart_ao_a";
1626 bias-disable;
1627 };
1628 };
1629
1630 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1631 mux {
1632 groups = "uart_ao_cts_a",
1633 "uart_ao_rts_a";
1634 function = "uart_ao_a";
1635 bias-disable;
1636 };
1637 };
1638
1639 uart_ao_b_pins: uart_ao_b {
1640 mux {
1641 groups = "uart_ao_tx_b",
1642 "uart_ao_rx_b";
1643 function = "uart_ao_b";
1644 bias-disable;
1645 };
1646 };
1647
1648 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1649 mux {
1650 groups = "uart_ao_cts_b",
1651 "uart_ao_rts_b";
1652 function = "uart_ao_b";
1653 bias-disable;
1654 };
1655 };
1656 };
1657
1658 sec_AO: ao-secure@140 {
1659 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1660 reg = <0x0 0x140 0x0 0x140>;
1661 amlogic,has-chip-id;
1662 };
1663
1664 pwm_AO_cd: pwm@2000 {
1665 compatible = "amlogic,meson-axg-ao-pwm";
1666 reg = <0x0 0x02000 0x0 0x20>;
1667 #pwm-cells = <3>;
1668 status = "disabled";
1669 };
1670
1671 uart_AO: serial@3000 {
1672 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1673 reg = <0x0 0x3000 0x0 0x18>;
1674 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1675 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1676 clock-names = "xtal", "pclk", "baud";
1677 status = "disabled";
1678 };
1679
1680 uart_AO_B: serial@4000 {
1681 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1682 reg = <0x0 0x4000 0x0 0x18>;
1683 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1684 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1685 clock-names = "xtal", "pclk", "baud";
1686 status = "disabled";
1687 };
1688
1689 i2c_AO: i2c@5000 {
1690 compatible = "amlogic,meson-axg-i2c";
1691 reg = <0x0 0x05000 0x0 0x20>;
1692 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1693 clocks = <&clkc CLKID_AO_I2C>;
1694 #address-cells = <1>;
1695 #size-cells = <0>;
1696 status = "disabled";
1697 };
1698
1699 pwm_AO_ab: pwm@7000 {
1700 compatible = "amlogic,meson-axg-ao-pwm";
1701 reg = <0x0 0x07000 0x0 0x20>;
1702 #pwm-cells = <3>;
1703 status = "disabled";
1704 };
1705
1706 ir: ir@8000 {
1707 compatible = "amlogic,meson-gxbb-ir";
1708 reg = <0x0 0x8000 0x0 0x20>;
1709 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1710 status = "disabled";
1711 };
1712
1713 saradc: adc@9000 {
1714 compatible = "amlogic,meson-axg-saradc",
1715 "amlogic,meson-saradc";
1716 reg = <0x0 0x9000 0x0 0x38>;
1717 #io-channel-cells = <1>;
1718 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1719 clocks = <&xtal>,
1720 <&clkc_AO CLKID_AO_SAR_ADC>,
1721 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1722 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1723 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1724 status = "disabled";
1725 };
1726 };
1727
1728 ge2d: ge2d@ff940000 {
1729 compatible = "amlogic,axg-ge2d";
1730 reg = <0x0 0xff940000 0x0 0x10000>;
1731 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1732 clocks = <&clkc CLKID_VAPB>;
1733 resets = <&reset RESET_GE2D>;
1734 };
1735
1736 gic: interrupt-controller@ffc01000 {
1737 compatible = "arm,gic-400";
1738 reg = <0x0 0xffc01000 0 0x1000>,
1739 <0x0 0xffc02000 0 0x2000>,
1740 <0x0 0xffc04000 0 0x2000>,
1741 <0x0 0xffc06000 0 0x2000>;
1742 interrupt-controller;
1743 interrupts = <GIC_PPI 9
1744 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1745 #interrupt-cells = <3>;
1746 #address-cells = <0>;
1747 };
1748
1749 cbus: bus@ffd00000 {
1750 compatible = "simple-bus";
1751 reg = <0x0 0xffd00000 0x0 0x25000>;
1752 #address-cells = <2>;
1753 #size-cells = <2>;
1754 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1755
1756 reset: reset-controller@1004 {
1757 compatible = "amlogic,meson-axg-reset";
1758 reg = <0x0 0x01004 0x0 0x9c>;
1759 #reset-cells = <1>;
1760 };
1761
1762 gpio_intc: interrupt-controller@f080 {
1763 compatible = "amlogic,meson-axg-gpio-intc",
1764 "amlogic,meson-gpio-intc";
1765 reg = <0x0 0xf080 0x0 0x10>;
1766 interrupt-controller;
1767 #interrupt-cells = <2>;
1768 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1769 };
1770
1771 watchdog@f0d0 {
1772 compatible = "amlogic,meson-gxbb-wdt";
1773 reg = <0x0 0xf0d0 0x0 0x10>;
1774 clocks = <&xtal>;
1775 };
1776
1777 pwm_ab: pwm@1b000 {
1778 compatible = "amlogic,meson-axg-ee-pwm";
1779 reg = <0x0 0x1b000 0x0 0x20>;
1780 #pwm-cells = <3>;
1781 status = "disabled";
1782 };
1783
1784 pwm_cd: pwm@1a000 {
1785 compatible = "amlogic,meson-axg-ee-pwm";
1786 reg = <0x0 0x1a000 0x0 0x20>;
1787 #pwm-cells = <3>;
1788 status = "disabled";
1789 };
1790
1791 spicc0: spi@13000 {
1792 compatible = "amlogic,meson-axg-spicc";
1793 reg = <0x0 0x13000 0x0 0x3c>;
1794 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1795 clocks = <&clkc CLKID_SPICC0>;
1796 clock-names = "core";
1797 #address-cells = <1>;
1798 #size-cells = <0>;
1799 status = "disabled";
1800 };
1801
1802 spicc1: spi@15000 {
1803 compatible = "amlogic,meson-axg-spicc";
1804 reg = <0x0 0x15000 0x0 0x3c>;
1805 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1806 clocks = <&clkc CLKID_SPICC1>;
1807 clock-names = "core";
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1810 status = "disabled";
1811 };
1812
1813 clk_msr: clock-measure@18000 {
1814 compatible = "amlogic,meson-axg-clk-measure";
1815 reg = <0x0 0x18000 0x0 0x10>;
1816 };
1817
1818 i2c3: i2c@1c000 {
1819 compatible = "amlogic,meson-axg-i2c";
1820 reg = <0x0 0x1c000 0x0 0x20>;
1821 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1822 clocks = <&clkc CLKID_I2C>;
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1825 status = "disabled";
1826 };
1827
1828 i2c2: i2c@1d000 {
1829 compatible = "amlogic,meson-axg-i2c";
1830 reg = <0x0 0x1d000 0x0 0x20>;
1831 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1832 clocks = <&clkc CLKID_I2C>;
1833 #address-cells = <1>;
1834 #size-cells = <0>;
1835 status = "disabled";
1836 };
1837
1838 i2c1: i2c@1e000 {
1839 compatible = "amlogic,meson-axg-i2c";
1840 reg = <0x0 0x1e000 0x0 0x20>;
1841 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1842 clocks = <&clkc CLKID_I2C>;
1843 #address-cells = <1>;
1844 #size-cells = <0>;
1845 status = "disabled";
1846 };
1847
1848 i2c0: i2c@1f000 {
1849 compatible = "amlogic,meson-axg-i2c";
1850 reg = <0x0 0x1f000 0x0 0x20>;
1851 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1852 clocks = <&clkc CLKID_I2C>;
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1855 status = "disabled";
1856 };
1857
1858 uart_B: serial@23000 {
1859 compatible = "amlogic,meson-gx-uart";
1860 reg = <0x0 0x23000 0x0 0x18>;
1861 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1862 status = "disabled";
1863 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1864 clock-names = "xtal", "pclk", "baud";
1865 };
1866
1867 uart_A: serial@24000 {
1868 compatible = "amlogic,meson-gx-uart";
1869 reg = <0x0 0x24000 0x0 0x18>;
1870 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1871 status = "disabled";
1872 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1873 clock-names = "xtal", "pclk", "baud";
1874 fifo-size = <128>;
1875 };
1876 };
1877
1878 apb: bus@ffe00000 {
1879 compatible = "simple-bus";
1880 reg = <0x0 0xffe00000 0x0 0x200000>;
1881 #address-cells = <2>;
1882 #size-cells = <2>;
1883 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1884
1885 sd_emmc_b: sd@5000 {
1886 compatible = "amlogic,meson-axg-mmc";
1887 reg = <0x0 0x5000 0x0 0x800>;
1888 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1889 status = "disabled";
1890 clocks = <&clkc CLKID_SD_EMMC_B>,
1891 <&clkc CLKID_SD_EMMC_B_CLK0>,
1892 <&clkc CLKID_FCLK_DIV2>;
1893 clock-names = "core", "clkin0", "clkin1";
1894 resets = <&reset RESET_SD_EMMC_B>;
1895 };
1896
1897 sd_emmc_c: mmc@7000 {
1898 compatible = "amlogic,meson-axg-mmc";
1899 reg = <0x0 0x7000 0x0 0x800>;
1900 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1901 status = "disabled";
1902 clocks = <&clkc CLKID_SD_EMMC_C>,
1903 <&clkc CLKID_SD_EMMC_C_CLK0>,
1904 <&clkc CLKID_FCLK_DIV2>;
1905 clock-names = "core", "clkin0", "clkin1";
1906 resets = <&reset RESET_SD_EMMC_C>;
1907 };
1908
1909 usb2_phy1: phy@9020 {
1910 compatible = "amlogic,meson-gxl-usb2-phy";
1911 #phy-cells = <0>;
1912 reg = <0x0 0x9020 0x0 0x20>;
1913 clocks = <&clkc CLKID_USB>;
1914 clock-names = "phy";
1915 resets = <&reset RESET_USB_OTG>;
1916 reset-names = "phy";
1917 };
1918 };
1919
1920 sram: sram@fffc0000 {
1921 compatible = "mmio-sram";
1922 reg = <0x0 0xfffc0000 0x0 0x20000>;
1923 #address-cells = <1>;
1924 #size-cells = <1>;
1925 ranges = <0 0x0 0xfffc0000 0x20000>;
1926
1927 cpu_scp_lpri: scp-sram@13000 {
1928 compatible = "amlogic,meson-axg-scp-shmem";
1929 reg = <0x13000 0x400>;
1930 };
1931
1932 cpu_scp_hpri: scp-sram@13400 {
1933 compatible = "amlogic,meson-axg-scp-shmem";
1934 reg = <0x13400 0x400>;
1935 };
1936 };
1937 };
1938
1939 timer {
1940 compatible = "arm,armv8-timer";
1941 interrupts = <GIC_PPI 13
1942 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1943 <GIC_PPI 14
1944 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1945 <GIC_PPI 11
1946 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1947 <GIC_PPI 10
1948 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1949 };
1950
1951 xtal: xtal-clk {
1952 compatible = "fixed-clock";
1953 clock-frequency = <24000000>;
1954 clock-output-names = "xtal";
1955 #clock-cells = <0>;
1956 };
1957 };
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