0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * DTS file for AMD Seattle XGBE (RevB)
0004 *
0005 * Copyright (C) 2015 Advanced Micro Devices, Inc.
0006 */
0007
0008 xgmacclk0_dma_250mhz: clk250mhz_0 {
0009 compatible = "fixed-clock";
0010 #clock-cells = <0>;
0011 clock-frequency = <250000000>;
0012 clock-output-names = "xgmacclk0_dma_250mhz";
0013 };
0014
0015 xgmacclk0_ptp_250mhz: clk250mhz_1 {
0016 compatible = "fixed-clock";
0017 #clock-cells = <0>;
0018 clock-frequency = <250000000>;
0019 clock-output-names = "xgmacclk0_ptp_250mhz";
0020 };
0021
0022 xgmacclk1_dma_250mhz: clk250mhz_2 {
0023 compatible = "fixed-clock";
0024 #clock-cells = <0>;
0025 clock-frequency = <250000000>;
0026 clock-output-names = "xgmacclk1_dma_250mhz";
0027 };
0028
0029 xgmacclk1_ptp_250mhz: clk250mhz_3 {
0030 compatible = "fixed-clock";
0031 #clock-cells = <0>;
0032 clock-frequency = <250000000>;
0033 clock-output-names = "xgmacclk1_ptp_250mhz";
0034 };
0035
0036 xgmac0: xgmac@e0700000 {
0037 compatible = "amd,xgbe-seattle-v1a";
0038 reg = <0 0xe0700000 0 0x80000>,
0039 <0 0xe0780000 0 0x80000>,
0040 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
0041 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
0042 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
0043 interrupts = <0 325 4>,
0044 <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
0045 <0 323 4>;
0046 amd,per-channel-interrupt;
0047 amd,speed-set = <0>;
0048 amd,serdes-blwc = <1>, <1>, <0>;
0049 amd,serdes-cdr-rate = <2>, <2>, <7>;
0050 amd,serdes-pq-skew = <10>, <10>, <18>;
0051 amd,serdes-tx-amp = <0>, <0>, <0>;
0052 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
0053 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
0054 mac-address = [ 02 A1 A2 A3 A4 A5 ];
0055 clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
0056 clock-names = "dma_clk", "ptp_clk";
0057 phy-mode = "xgmii";
0058 iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
0059 dma-coherent;
0060 };
0061
0062 xgmac1: xgmac@e0900000 {
0063 compatible = "amd,xgbe-seattle-v1a";
0064 reg = <0 0xe0900000 0 0x80000>,
0065 <0 0xe0980000 0 0x80000>,
0066 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
0067 <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
0068 <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
0069 interrupts = <0 324 4>,
0070 <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
0071 <0 322 4>;
0072 amd,per-channel-interrupt;
0073 amd,speed-set = <0>;
0074 amd,serdes-blwc = <1>, <1>, <0>;
0075 amd,serdes-cdr-rate = <2>, <2>, <7>;
0076 amd,serdes-pq-skew = <10>, <10>, <18>;
0077 amd,serdes-tx-amp = <0>, <0>, <0>;
0078 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
0079 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
0080 mac-address = [ 02 B1 B2 B3 B4 B5 ];
0081 clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
0082 clock-names = "dma_clk", "ptp_clk";
0083 phy-mode = "xgmii";
0084 iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
0085 dma-coherent;
0086 };
0087
0088 xgmac0_smmu: iommu@e0600000 {
0089 compatible = "arm,mmu-401";
0090 reg = <0 0xe0600000 0 0x10000>;
0091 #global-interrupts = <1>;
0092 interrupts = /* Uses combined intr for both
0093 * global and context
0094 */
0095 <0 336 4>,
0096 <0 336 4>;
0097 #iommu-cells = <2>;
0098 dma-coherent;
0099 };
0100
0101 xgmac1_smmu: iommu@e0800000 {
0102 compatible = "arm,mmu-401";
0103 reg = <0 0xe0800000 0 0x10000>;
0104 #global-interrupts = <1>;
0105 interrupts = /* Uses combined intr for both
0106 * global and context
0107 */
0108 <0 335 4>,
0109 <0 335 4>;
0110 #iommu-cells = <2>;
0111 dma-coherent;
0112 };
