0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * DTS file for AMD Seattle SoC
0004 *
0005 * Copyright (C) 2014 Advanced Micro Devices, Inc.
0006 */
0007
0008 / {
0009 compatible = "amd,seattle";
0010 interrupt-parent = <&gic0>;
0011 #address-cells = <2>;
0012 #size-cells = <2>;
0013
0014 gic0: interrupt-controller@e1101000 {
0015 compatible = "arm,gic-400", "arm,cortex-a15-gic";
0016 interrupt-controller;
0017 #interrupt-cells = <3>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020 reg = <0x0 0xe1110000 0 0x1000>,
0021 <0x0 0xe112f000 0 0x2000>,
0022 <0x0 0xe1140000 0 0x2000>,
0023 <0x0 0xe1160000 0 0x2000>;
0024 interrupts = <1 9 0xf04>;
0025 ranges = <0 0 0 0xe1100000 0 0x100000>;
0026 v2m0: v2m@e0080000 {
0027 compatible = "arm,gic-v2m-frame";
0028 msi-controller;
0029 reg = <0x0 0x00080000 0 0x1000>;
0030 };
0031 };
0032
0033 timer {
0034 compatible = "arm,armv8-timer";
0035 interrupts = <1 13 0xff04>,
0036 <1 14 0xff04>,
0037 <1 11 0xff04>,
0038 <1 10 0xff04>;
0039 };
0040
0041 smb0: smb {
0042 compatible = "simple-bus";
0043 #address-cells = <2>;
0044 #size-cells = <2>;
0045 ranges;
0046
0047 /*
0048 * dma-ranges is 40-bit address space containing:
0049 * - GICv2m MSI register is at 0xe0080000
0050 * - DRAM range [0x8000000000 to 0xffffffffff]
0051 */
0052 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
0053
0054 /include/ "amd-seattle-clks.dtsi"
0055
0056 sata0: sata@e0300000 {
0057 compatible = "snps,dwc-ahci";
0058 reg = <0 0xe0300000 0 0xf0000>;
0059 interrupts = <0 355 4>;
0060 clocks = <&sataclk_333mhz>;
0061 iommus = <&sata0_smmu 0x0 0x1f>;
0062 dma-coherent;
0063 };
0064
0065 /* This is for Rev B only */
0066 sata1: sata@e0d00000 {
0067 status = "disabled";
0068 compatible = "snps,dwc-ahci";
0069 reg = <0 0xe0d00000 0 0xf0000>;
0070 interrupts = <0 354 4>;
0071 clocks = <&sataclk_333mhz>;
0072 iommus = <&sata1_smmu 0x0e>,
0073 <&sata1_smmu 0x0f>,
0074 <&sata1_smmu 0x1e>;
0075 dma-coherent;
0076 };
0077
0078 sata0_smmu: iommu@e0200000 {
0079 compatible = "arm,mmu-401";
0080 reg = <0 0xe0200000 0 0x10000>;
0081 #global-interrupts = <1>;
0082 interrupts = <0 332 4>, <0 332 4>;
0083 #iommu-cells = <2>;
0084 dma-coherent;
0085 };
0086
0087 sata1_smmu: iommu@e0c00000 {
0088 compatible = "arm,mmu-401";
0089 reg = <0 0xe0c00000 0 0x10000>;
0090 #global-interrupts = <1>;
0091 interrupts = <0 331 4>, <0 331 4>;
0092 #iommu-cells = <1>;
0093 dma-coherent;
0094 };
0095
0096 i2c0: i2c@e1000000 {
0097 status = "disabled";
0098 compatible = "snps,designware-i2c";
0099 reg = <0 0xe1000000 0 0x1000>;
0100 interrupts = <0 357 4>;
0101 clocks = <&miscclk_250mhz>;
0102 };
0103
0104 i2c1: i2c@e0050000 {
0105 status = "disabled";
0106 compatible = "snps,designware-i2c";
0107 reg = <0 0xe0050000 0 0x1000>;
0108 interrupts = <0 340 4>;
0109 clocks = <&miscclk_250mhz>;
0110 };
0111
0112 serial0: serial@e1010000 {
0113 compatible = "arm,pl011", "arm,primecell";
0114 reg = <0 0xe1010000 0 0x1000>;
0115 interrupts = <0 328 4>;
0116 clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
0117 clock-names = "uartclk", "apb_pclk";
0118 };
0119
0120 spi0: spi@e1020000 {
0121 status = "disabled";
0122 compatible = "arm,pl022", "arm,primecell";
0123 reg = <0 0xe1020000 0 0x1000>;
0124 spi-controller;
0125 interrupts = <0 330 4>;
0126 clocks = <&uartspiclk_100mhz>;
0127 clock-names = "apb_pclk";
0128 };
0129
0130 spi1: spi@e1030000 {
0131 status = "disabled";
0132 compatible = "arm,pl022", "arm,primecell";
0133 reg = <0 0xe1030000 0 0x1000>;
0134 spi-controller;
0135 interrupts = <0 329 4>;
0136 clocks = <&uartspiclk_100mhz>;
0137 clock-names = "apb_pclk";
0138 num-cs = <1>;
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141 };
0142
0143 gpio0: gpio@e1040000 { /* Not available to OS for B0 */
0144 status = "disabled";
0145 compatible = "arm,pl061", "arm,primecell";
0146 #gpio-cells = <2>;
0147 reg = <0 0xe1040000 0 0x1000>;
0148 gpio-controller;
0149 interrupts = <0 359 4>;
0150 interrupt-controller;
0151 #interrupt-cells = <2>;
0152 clocks = <&miscclk_250mhz>;
0153 clock-names = "apb_pclk";
0154 };
0155
0156 gpio1: gpio@e1050000 { /* [0:7] */
0157 status = "disabled";
0158 compatible = "arm,pl061", "arm,primecell";
0159 #gpio-cells = <2>;
0160 reg = <0 0xe1050000 0 0x1000>;
0161 gpio-controller;
0162 interrupt-controller;
0163 #interrupt-cells = <2>;
0164 interrupts = <0 358 4>;
0165 clocks = <&miscclk_250mhz>;
0166 clock-names = "apb_pclk";
0167 };
0168
0169 gpio2: gpio@e0020000 { /* [8:15] */
0170 status = "disabled";
0171 compatible = "arm,pl061", "arm,primecell";
0172 #gpio-cells = <2>;
0173 reg = <0 0xe0020000 0 0x1000>;
0174 gpio-controller;
0175 interrupt-controller;
0176 #interrupt-cells = <2>;
0177 interrupts = <0 366 4>;
0178 clocks = <&miscclk_250mhz>;
0179 clock-names = "apb_pclk";
0180 };
0181
0182 gpio3: gpio@e0030000 { /* [16:23] */
0183 status = "disabled";
0184 compatible = "arm,pl061", "arm,primecell";
0185 #gpio-cells = <2>;
0186 reg = <0 0xe0030000 0 0x1000>;
0187 gpio-controller;
0188 interrupt-controller;
0189 #interrupt-cells = <2>;
0190 interrupts = <0 365 4>;
0191 clocks = <&miscclk_250mhz>;
0192 clock-names = "apb_pclk";
0193 };
0194
0195 gpio4: gpio@e0080000 { /* [24] */
0196 status = "disabled";
0197 compatible = "arm,pl061", "arm,primecell";
0198 #gpio-cells = <2>;
0199 reg = <0 0xe0080000 0 0x1000>;
0200 gpio-controller;
0201 interrupt-controller;
0202 #interrupt-cells = <2>;
0203 interrupts = <0 361 4>;
0204 clocks = <&miscclk_250mhz>;
0205 clock-names = "apb_pclk";
0206 };
0207
0208 ccp0: ccp@e0100000 {
0209 status = "disabled";
0210 compatible = "amd,ccp-seattle-v1a";
0211 reg = <0 0xe0100000 0 0x10000>;
0212 interrupts = <0 3 4>;
0213 dma-coherent;
0214 iommus = <&sata1_smmu 0x00>,
0215 <&sata1_smmu 0x02>,
0216 <&sata1_smmu 0x40>,
0217 <&sata1_smmu 0x42>;
0218 };
0219
0220 pcie0: pcie@f0000000 {
0221 compatible = "pci-host-ecam-generic";
0222 #address-cells = <3>;
0223 #size-cells = <2>;
0224 #interrupt-cells = <1>;
0225 device_type = "pci";
0226 bus-range = <0 0x7f>;
0227 msi-parent = <&v2m0>;
0228 reg = <0 0xf0000000 0 0x10000000>;
0229
0230 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
0231 interrupt-map =
0232 <0x1100 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
0233 <0x1100 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
0234 <0x1100 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
0235 <0x1100 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>,
0236
0237 <0x1200 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x124 0x1>,
0238 <0x1200 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x125 0x1>,
0239 <0x1200 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x126 0x1>,
0240 <0x1200 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x127 0x1>,
0241
0242 <0x1300 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x128 0x1>,
0243 <0x1300 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x129 0x1>,
0244 <0x1300 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x12a 0x1>,
0245 <0x1300 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x12b 0x1>;
0246
0247 dma-coherent;
0248 dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
0249 ranges =
0250 /* I/O Memory (size=64K) */
0251 <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
0252 /* 32-bit MMIO (size=2G) */
0253 <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
0254 /* 64-bit MMIO (size= 508G) */
0255 <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
0256 iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
0257 };
0258
0259 pcie_smmu: iommu@e0a00000 {
0260 compatible = "arm,mmu-401";
0261 reg = <0 0xe0a00000 0 0x10000>;
0262 #global-interrupts = <1>;
0263 interrupts = <0 333 4>, <0 333 4>;
0264 #iommu-cells = <1>;
0265 dma-coherent;
0266 };
0267
0268 /* Perf CCN504 PMU */
0269 ccn: ccn@e8000000 {
0270 compatible = "arm,ccn-504";
0271 reg = <0x0 0xe8000000 0 0x1000000>;
0272 interrupts = <0 380 4>;
0273 };
0274
0275 ipmi_kcs: kcs@e0010000 {
0276 status = "disabled";
0277 compatible = "ipmi-kcs";
0278 device_type = "ipmi";
0279 reg = <0x0 0xe0010000 0 0x8>;
0280 interrupts = <0 389 4>;
0281 reg-size = <1>;
0282 reg-spacing = <4>;
0283 };
0284 };
0285 };
