OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 / {
0004 cpus {
0005 #address-cells = <0x1>;
0006 #size-cells = <0x0>;
0007
0008 cpu-map {
0009 cluster0 {
0010 core0 {
0011 cpu = <&CPU0>;
0012 };
0013 core1 {
0014 cpu = <&CPU1>;
0015 };
0016 };
0017 cluster1 {
0018 core0 {
0019 cpu = <&CPU2>;
0020 };
0021 core1 {
0022 cpu = <&CPU3>;
0023 };
0024 };
0025 cluster2 {
0026 core0 {
0027 cpu = <&CPU4>;
0028 };
0029 core1 {
0030 cpu = <&CPU5>;
0031 };
0032 };
0033 cluster3 {
0034 core0 {
0035 cpu = <&CPU6>;
0036 };
0037 core1 {
0038 cpu = <&CPU7>;
0039 };
0040 };
0041 };
0042
0043 CPU0: cpu@0 {
0044 device_type = "cpu";
0045 compatible = "arm,cortex-a57";
0046 reg = <0x0>;
0047 enable-method = "psci";
0048
0049 i-cache-size = <0xC000>;
0050 i-cache-line-size = <64>;
0051 i-cache-sets = <256>;
0052 d-cache-size = <0x8000>;
0053 d-cache-line-size = <64>;
0054 d-cache-sets = <256>;
0055 l2-cache = <&L2_0>;
0056
0057 };
0058
0059 CPU1: cpu@1 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a57";
0062 reg = <0x1>;
0063 enable-method = "psci";
0064
0065 i-cache-size = <0xC000>;
0066 i-cache-line-size = <64>;
0067 i-cache-sets = <256>;
0068 d-cache-size = <0x8000>;
0069 d-cache-line-size = <64>;
0070 d-cache-sets = <256>;
0071 l2-cache = <&L2_0>;
0072 };
0073
0074 CPU2: cpu@100 {
0075 device_type = "cpu";
0076 compatible = "arm,cortex-a57";
0077 reg = <0x100>;
0078 enable-method = "psci";
0079
0080 i-cache-size = <0xC000>;
0081 i-cache-line-size = <64>;
0082 i-cache-sets = <256>;
0083 d-cache-size = <0x8000>;
0084 d-cache-line-size = <64>;
0085 d-cache-sets = <256>;
0086 l2-cache = <&L2_1>;
0087 };
0088
0089 CPU3: cpu@101 {
0090 device_type = "cpu";
0091 compatible = "arm,cortex-a57";
0092 reg = <0x101>;
0093 enable-method = "psci";
0094
0095 i-cache-size = <0xC000>;
0096 i-cache-line-size = <64>;
0097 i-cache-sets = <256>;
0098 d-cache-size = <0x8000>;
0099 d-cache-line-size = <64>;
0100 d-cache-sets = <256>;
0101 l2-cache = <&L2_1>;
0102 };
0103
0104 CPU4: cpu@200 {
0105 device_type = "cpu";
0106 compatible = "arm,cortex-a57";
0107 reg = <0x200>;
0108 enable-method = "psci";
0109
0110 i-cache-size = <0xC000>;
0111 i-cache-line-size = <64>;
0112 i-cache-sets = <256>;
0113 d-cache-size = <0x8000>;
0114 d-cache-line-size = <64>;
0115 d-cache-sets = <256>;
0116 l2-cache = <&L2_2>;
0117 };
0118
0119 CPU5: cpu@201 {
0120 device_type = "cpu";
0121 compatible = "arm,cortex-a57";
0122 reg = <0x201>;
0123 enable-method = "psci";
0124
0125 i-cache-size = <0xC000>;
0126 i-cache-line-size = <64>;
0127 i-cache-sets = <256>;
0128 d-cache-size = <0x8000>;
0129 d-cache-line-size = <64>;
0130 d-cache-sets = <256>;
0131 l2-cache = <&L2_2>;
0132 };
0133
0134 CPU6: cpu@300 {
0135 device_type = "cpu";
0136 compatible = "arm,cortex-a57";
0137 reg = <0x300>;
0138 enable-method = "psci";
0139
0140 i-cache-size = <0xC000>;
0141 i-cache-line-size = <64>;
0142 i-cache-sets = <256>;
0143 d-cache-size = <0x8000>;
0144 d-cache-line-size = <64>;
0145 d-cache-sets = <256>;
0146 l2-cache = <&L2_3>;
0147 };
0148
0149 CPU7: cpu@301 {
0150 device_type = "cpu";
0151 compatible = "arm,cortex-a57";
0152 reg = <0x301>;
0153 enable-method = "psci";
0154
0155 i-cache-size = <0xC000>;
0156 i-cache-line-size = <64>;
0157 i-cache-sets = <256>;
0158 d-cache-size = <0x8000>;
0159 d-cache-line-size = <64>;
0160 d-cache-sets = <256>;
0161 l2-cache = <&L2_3>;
0162 };
0163 };
0164
0165 L2_0: l2-cache0 {
0166 cache-size = <0x100000>;
0167 cache-line-size = <64>;
0168 cache-sets = <1024>;
0169 cache-unified;
0170 next-level-cache = <&L3>;
0171 };
0172
0173 L2_1: l2-cache1 {
0174 cache-size = <0x100000>;
0175 cache-line-size = <64>;
0176 cache-sets = <1024>;
0177 cache-unified;
0178 next-level-cache = <&L3>;
0179 };
0180
0181 L2_2: l2-cache2 {
0182 cache-size = <0x100000>;
0183 cache-line-size = <64>;
0184 cache-sets = <1024>;
0185 cache-unified;
0186 next-level-cache = <&L3>;
0187 };
0188
0189 L2_3: l2-cache3 {
0190 cache-size = <0x100000>;
0191 cache-line-size = <64>;
0192 cache-sets = <1024>;
0193 cache-unified;
0194 next-level-cache = <&L3>;
0195 };
0196
0197 L3: l3-cache {
0198 cache-level = <3>;
0199 cache-size = <0x800000>;
0200 cache-line-size = <64>;
0201 cache-sets = <8192>;
0202 cache-unified;
0203 };
0204
0205 pmu {
0206 compatible = "arm,cortex-a57-pmu";
0207 interrupts = <0x0 0x7 0x4>,
0208 <0x0 0x8 0x4>,
0209 <0x0 0x9 0x4>,
0210 <0x0 0xa 0x4>,
0211 <0x0 0xb 0x4>,
0212 <0x0 0xc 0x4>,
0213 <0x0 0xd 0x4>,
0214 <0x0 0xe 0x4>;
0215 interrupt-affinity = <&CPU0>,
0216 <&CPU1>,
0217 <&CPU2>,
0218 <&CPU3>,
0219 <&CPU4>,
0220 <&CPU5>,
0221 <&CPU6>,
0222 <&CPU7>;
0223 };
0224 };
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