0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009
0010 / {
0011 model = "Amazon's Annapurna Labs Alpine v3";
0012 compatible = "amazon,al-alpine-v3";
0013
0014 interrupt-parent = <&gic>;
0015
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 cpus {
0020 #address-cells = <1>;
0021 #size-cells = <0>;
0022
0023 cpu@0 {
0024 device_type = "cpu";
0025 compatible = "arm,cortex-a72";
0026 reg = <0x0>;
0027 enable-method = "psci";
0028 d-cache-size = <0x8000>;
0029 d-cache-line-size = <64>;
0030 d-cache-sets = <256>;
0031 i-cache-size = <0xc000>;
0032 i-cache-line-size = <64>;
0033 i-cache-sets = <256>;
0034 next-level-cache = <&cluster0_l2>;
0035 };
0036
0037 cpu@1 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a72";
0040 reg = <0x1>;
0041 enable-method = "psci";
0042 d-cache-size = <0x8000>;
0043 d-cache-line-size = <64>;
0044 d-cache-sets = <256>;
0045 i-cache-size = <0xc000>;
0046 i-cache-line-size = <64>;
0047 i-cache-sets = <256>;
0048 next-level-cache = <&cluster0_l2>;
0049 };
0050
0051 cpu@2 {
0052 device_type = "cpu";
0053 compatible = "arm,cortex-a72";
0054 reg = <0x2>;
0055 enable-method = "psci";
0056 d-cache-size = <0x8000>;
0057 d-cache-line-size = <64>;
0058 d-cache-sets = <256>;
0059 i-cache-size = <0xc000>;
0060 i-cache-line-size = <64>;
0061 i-cache-sets = <256>;
0062 next-level-cache = <&cluster0_l2>;
0063 };
0064
0065 cpu@3 {
0066 device_type = "cpu";
0067 compatible = "arm,cortex-a72";
0068 reg = <0x3>;
0069 enable-method = "psci";
0070 d-cache-size = <0x8000>;
0071 d-cache-line-size = <64>;
0072 d-cache-sets = <256>;
0073 i-cache-size = <0xc000>;
0074 i-cache-line-size = <64>;
0075 i-cache-sets = <256>;
0076 next-level-cache = <&cluster0_l2>;
0077 };
0078
0079 cpu@100 {
0080 device_type = "cpu";
0081 compatible = "arm,cortex-a72";
0082 reg = <0x100>;
0083 enable-method = "psci";
0084 d-cache-size = <0x8000>;
0085 d-cache-line-size = <64>;
0086 d-cache-sets = <256>;
0087 i-cache-size = <0xc000>;
0088 i-cache-line-size = <64>;
0089 i-cache-sets = <256>;
0090 next-level-cache = <&cluster1_l2>;
0091 };
0092
0093 cpu@101 {
0094 device_type = "cpu";
0095 compatible = "arm,cortex-a72";
0096 reg = <0x101>;
0097 enable-method = "psci";
0098 d-cache-size = <0x8000>;
0099 d-cache-line-size = <64>;
0100 d-cache-sets = <256>;
0101 i-cache-size = <0xc000>;
0102 i-cache-line-size = <64>;
0103 i-cache-sets = <256>;
0104 next-level-cache = <&cluster1_l2>;
0105 };
0106
0107 cpu@102 {
0108 device_type = "cpu";
0109 compatible = "arm,cortex-a72";
0110 reg = <0x102>;
0111 enable-method = "psci";
0112 d-cache-size = <0x8000>;
0113 d-cache-line-size = <64>;
0114 d-cache-sets = <256>;
0115 i-cache-size = <0xc000>;
0116 i-cache-line-size = <64>;
0117 i-cache-sets = <256>;
0118 next-level-cache = <&cluster1_l2>;
0119 };
0120
0121 cpu@103 {
0122 device_type = "cpu";
0123 compatible = "arm,cortex-a72";
0124 reg = <0x103>;
0125 enable-method = "psci";
0126 d-cache-size = <0x8000>;
0127 d-cache-line-size = <64>;
0128 d-cache-sets = <256>;
0129 i-cache-size = <0xc000>;
0130 i-cache-line-size = <64>;
0131 i-cache-sets = <256>;
0132 next-level-cache = <&cluster1_l2>;
0133 };
0134
0135 cpu@200 {
0136 device_type = "cpu";
0137 compatible = "arm,cortex-a72";
0138 reg = <0x200>;
0139 enable-method = "psci";
0140 d-cache-size = <0x8000>;
0141 d-cache-line-size = <64>;
0142 d-cache-sets = <256>;
0143 i-cache-size = <0xc000>;
0144 i-cache-line-size = <64>;
0145 i-cache-sets = <256>;
0146 next-level-cache = <&cluster2_l2>;
0147 };
0148
0149 cpu@201 {
0150 device_type = "cpu";
0151 compatible = "arm,cortex-a72";
0152 reg = <0x201>;
0153 enable-method = "psci";
0154 d-cache-size = <0x8000>;
0155 d-cache-line-size = <64>;
0156 d-cache-sets = <256>;
0157 i-cache-size = <0xc000>;
0158 i-cache-line-size = <64>;
0159 i-cache-sets = <256>;
0160 next-level-cache = <&cluster2_l2>;
0161 };
0162
0163 cpu@202 {
0164 device_type = "cpu";
0165 compatible = "arm,cortex-a72";
0166 reg = <0x202>;
0167 enable-method = "psci";
0168 d-cache-size = <0x8000>;
0169 d-cache-line-size = <64>;
0170 d-cache-sets = <256>;
0171 i-cache-size = <0xc000>;
0172 i-cache-line-size = <64>;
0173 i-cache-sets = <256>;
0174 next-level-cache = <&cluster2_l2>;
0175 };
0176
0177 cpu@203 {
0178 device_type = "cpu";
0179 compatible = "arm,cortex-a72";
0180 reg = <0x203>;
0181 enable-method = "psci";
0182 d-cache-size = <0x8000>;
0183 d-cache-line-size = <64>;
0184 d-cache-sets = <256>;
0185 i-cache-size = <0xc000>;
0186 i-cache-line-size = <64>;
0187 i-cache-sets = <256>;
0188 next-level-cache = <&cluster2_l2>;
0189 };
0190
0191 cpu@300 {
0192 device_type = "cpu";
0193 compatible = "arm,cortex-a72";
0194 reg = <0x300>;
0195 enable-method = "psci";
0196 d-cache-size = <0x8000>;
0197 d-cache-line-size = <64>;
0198 d-cache-sets = <256>;
0199 i-cache-size = <0xc000>;
0200 i-cache-line-size = <64>;
0201 i-cache-sets = <256>;
0202 next-level-cache = <&cluster3_l2>;
0203 };
0204
0205 cpu@301 {
0206 device_type = "cpu";
0207 compatible = "arm,cortex-a72";
0208 reg = <0x301>;
0209 enable-method = "psci";
0210 d-cache-size = <0x8000>;
0211 d-cache-line-size = <64>;
0212 d-cache-sets = <256>;
0213 i-cache-size = <0xc000>;
0214 i-cache-line-size = <64>;
0215 i-cache-sets = <256>;
0216 next-level-cache = <&cluster3_l2>;
0217 };
0218
0219 cpu@302 {
0220 device_type = "cpu";
0221 compatible = "arm,cortex-a72";
0222 reg = <0x302>;
0223 enable-method = "psci";
0224 d-cache-size = <0x8000>;
0225 d-cache-line-size = <64>;
0226 d-cache-sets = <256>;
0227 i-cache-size = <0xc000>;
0228 i-cache-line-size = <64>;
0229 i-cache-sets = <256>;
0230 next-level-cache = <&cluster3_l2>;
0231 };
0232
0233 cpu@303 {
0234 device_type = "cpu";
0235 compatible = "arm,cortex-a72";
0236 reg = <0x303>;
0237 enable-method = "psci";
0238 d-cache-size = <0x8000>;
0239 d-cache-line-size = <64>;
0240 d-cache-sets = <256>;
0241 i-cache-size = <0xc000>;
0242 i-cache-line-size = <64>;
0243 i-cache-sets = <256>;
0244 next-level-cache = <&cluster3_l2>;
0245 };
0246
0247 cluster0_l2: cache@0 {
0248 compatible = "cache";
0249 cache-size = <0x200000>;
0250 cache-line-size = <64>;
0251 cache-sets = <2048>;
0252 cache-level = <2>;
0253 };
0254
0255 cluster1_l2: cache@100 {
0256 compatible = "cache";
0257 cache-size = <0x200000>;
0258 cache-line-size = <64>;
0259 cache-sets = <2048>;
0260 cache-level = <2>;
0261 };
0262
0263 cluster2_l2: cache@200 {
0264 compatible = "cache";
0265 cache-size = <0x200000>;
0266 cache-line-size = <64>;
0267 cache-sets = <2048>;
0268 cache-level = <2>;
0269 };
0270
0271 cluster3_l2: cache@300 {
0272 compatible = "cache";
0273 cache-size = <0x200000>;
0274 cache-line-size = <64>;
0275 cache-sets = <2048>;
0276 cache-level = <2>;
0277 };
0278
0279 };
0280
0281 reserved-memory {
0282 #address-cells = <2>;
0283 #size-cells = <2>;
0284 ranges;
0285
0286 secmon@0 {
0287 reg = <0x0 0x0 0x0 0x100000>;
0288 no-map;
0289 };
0290 };
0291
0292 psci {
0293 compatible = "arm,psci-0.2";
0294 method = "smc";
0295 };
0296
0297 timer {
0298 compatible = "arm,armv8-timer";
0299 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0300 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0301 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0302 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0303 };
0304
0305 pmu {
0306 compatible = "arm,cortex-a72-pmu";
0307 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0308 };
0309
0310
0311 soc {
0312 compatible = "simple-bus";
0313 #address-cells = <2>;
0314 #size-cells = <2>;
0315 ranges;
0316
0317 gic: interrupt-controller@f0000000 {
0318 compatible = "arm,gic-v3";
0319 #interrupt-cells = <3>;
0320 interrupt-controller;
0321 reg = <0x0 0xf0800000 0 0x10000>, /* GICD */
0322 <0x0 0xf0a00000 0 0x200000>, /* GICR */
0323 <0x0 0xf0000000 0 0x2000>, /* GICC */
0324 <0x0 0xf0010000 0 0x1000>, /* GICH */
0325 <0x0 0xf0020000 0 0x2000>; /* GICV */
0326 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0327 };
0328
0329 pcie@fbd00000 {
0330 compatible = "pci-host-ecam-generic";
0331 device_type = "pci";
0332 #size-cells = <2>;
0333 #address-cells = <3>;
0334 #interrupt-cells = <1>;
0335 reg = <0x0 0xfbd00000 0x0 0x100000>;
0336 interrupt-map-mask = <0xf800 0 0 7>;
0337 /* 8 x legacy interrupts for SATA only */
0338 interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
0339 <0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>,
0340 <0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>,
0341 <0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>,
0342 <0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>,
0343 <0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>,
0344 <0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>,
0345 <0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>;
0346 ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
0347 bus-range = <0x00 0x00>;
0348 msi-parent = <&msix>;
0349 };
0350
0351 msix: msix@fbe00000 {
0352 compatible = "al,alpine-msix";
0353 reg = <0x0 0xfbe00000 0x0 0x100000>;
0354 interrupt-controller;
0355 msi-controller;
0356 al,msi-base-spi = <336>;
0357 al,msi-num-spis = <959>;
0358 interrupt-parent = <&gic>;
0359 };
0360
0361 io-fabric {
0362 compatible = "simple-bus";
0363 #address-cells = <1>;
0364 #size-cells = <1>;
0365 ranges = <0x0 0x0 0xfc000000 0x2000000>;
0366
0367 uart0: serial@1883000 {
0368 compatible = "ns16550a";
0369 reg = <0x1883000 0x1000>;
0370 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0371 clock-frequency = <0>; /* Filled by firmware */
0372 reg-shift = <2>;
0373 reg-io-width = <4>;
0374 status = "disabled";
0375 };
0376
0377 uart1: serial@1884000 {
0378 compatible = "ns16550a";
0379 reg = <0x1884000 0x1000>;
0380 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0381 clock-frequency = <0>; /* Filled by firmware */
0382 reg-shift = <2>;
0383 reg-io-width = <4>;
0384 status = "disabled";
0385 };
0386
0387 uart2: serial@1885000 {
0388 compatible = "ns16550a";
0389 reg = <0x1885000 0x1000>;
0390 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0391 clock-frequency = <0>; /* Filled by firmware */
0392 reg-shift = <2>;
0393 reg-io-width = <4>;
0394 status = "disabled";
0395 };
0396
0397 uart3: serial@1886000 {
0398 compatible = "ns16550a";
0399 reg = <0x1886000 0x1000>;
0400 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0401 clock-frequency = <0>; /* Filled by firmware */
0402 reg-shift = <2>;
0403 reg-io-width = <4>;
0404 status = "disabled";
0405 };
0406 };
0407 };
0408 };
