0001 /*
0002 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
0003 *
0004 * Antoine Tenart <antoine.tenart@free-electrons.com>
0005 *
0006 * This software is available to you under a choice of one of two
0007 * licenses. You may choose to be licensed under the terms of the GNU
0008 * General Public License (GPL) Version 2, available from the file
0009 * COPYING in the main directory of this source tree, or the
0010 * BSD license below:
0011 *
0012 * Redistribution and use in source and binary forms, with or
0013 * without modification, are permitted provided that the following
0014 * conditions are met:
0015 *
0016 * - Redistributions of source code must retain the above
0017 * copyright notice, this list of conditions and the following
0018 * disclaimer.
0019 *
0020 * - Redistributions in binary form must reproduce the above
0021 * copyright notice, this list of conditions and the following
0022 * disclaimer in the documentation and/or other materials
0023 * provided with the distribution.
0024 *
0025 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0026 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0027 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0028 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0029 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0030 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0031 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0032 * SOFTWARE.
0033 */
0034
0035 /dts-v1/;
0036
0037 #include <dt-bindings/interrupt-controller/arm-gic.h>
0038
0039 / {
0040 model = "Annapurna Labs Alpine v2";
0041 compatible = "al,alpine-v2";
0042 #address-cells = <2>;
0043 #size-cells = <2>;
0044
0045 cpus {
0046 #address-cells = <2>;
0047 #size-cells = <0>;
0048
0049 cpu@0 {
0050 compatible = "arm,cortex-a57";
0051 device_type = "cpu";
0052 reg = <0x0 0x0>;
0053 enable-method = "psci";
0054 };
0055
0056 cpu@1 {
0057 compatible = "arm,cortex-a57";
0058 device_type = "cpu";
0059 reg = <0x0 0x1>;
0060 enable-method = "psci";
0061 };
0062
0063 cpu@2 {
0064 compatible = "arm,cortex-a57";
0065 device_type = "cpu";
0066 reg = <0x0 0x2>;
0067 enable-method = "psci";
0068 };
0069
0070 cpu@3 {
0071 compatible = "arm,cortex-a57";
0072 device_type = "cpu";
0073 reg = <0x0 0x3>;
0074 enable-method = "psci";
0075 };
0076 };
0077
0078 psci {
0079 compatible = "arm,psci-0.2", "arm,psci";
0080 method = "smc";
0081 cpu_suspend = <0x84000001>;
0082 cpu_off = <0x84000002>;
0083 cpu_on = <0x84000003>;
0084 };
0085
0086 sbclk: sbclk {
0087 compatible = "fixed-clock";
0088 #clock-cells = <0>;
0089 clock-frequency = <1000000>;
0090 };
0091
0092 soc {
0093 compatible = "simple-bus";
0094 #address-cells = <2>;
0095 #size-cells = <2>;
0096
0097 interrupt-parent = <&gic>;
0098 ranges;
0099
0100 timer {
0101 compatible = "arm,armv8-timer";
0102 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0103 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0104 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0105 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0106 };
0107
0108 pmu {
0109 compatible = "arm,armv8-pmuv3";
0110 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0113 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0114 };
0115
0116 gic: interrupt-controller@f0200000 {
0117 compatible = "arm,gic-v3";
0118 reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */
0119 <0x0 0xf0280000 0x0 0x200000>, /* GICR */
0120 <0x0 0xf0100000 0x0 0x2000>, /* GICC */
0121 <0x0 0xf0110000 0x0 0x2000>, /* GICV */
0122 <0x0 0xf0120000 0x0 0x2000>; /* GICH */
0123 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0124 interrupt-controller;
0125 #interrupt-cells = <3>;
0126 };
0127
0128 pci@fbc00000 {
0129 compatible = "pci-host-ecam-generic";
0130 device_type = "pci";
0131 #size-cells = <2>;
0132 #address-cells = <3>;
0133 #interrupt-cells = <1>;
0134 reg = <0x0 0xfbc00000 0x0 0x100000>;
0135 interrupt-map-mask = <0xf800 0 0 7>;
0136 /* add legacy interrupts for SATA only */
0137 interrupt-map = <0x4000 0 0 1 &gic 0 53 4>,
0138 <0x4800 0 0 1 &gic 0 54 4>;
0139 /* 32 bit non prefetchable memory space */
0140 ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
0141 bus-range = <0x00 0x00>;
0142 msi-parent = <&msix>;
0143 };
0144
0145 msix: msix@fbe00000 {
0146 compatible = "al,alpine-msix";
0147 reg = <0x0 0xfbe00000 0x0 0x100000>;
0148 interrupt-controller;
0149 msi-controller;
0150 al,msi-base-spi = <160>;
0151 al,msi-num-spis = <160>;
0152 };
0153
0154 io-fabric {
0155 compatible = "simple-bus";
0156 #address-cells = <1>;
0157 #size-cells = <1>;
0158 ranges = <0x0 0x0 0xfc000000 0x2000000>;
0159
0160 uart0: serial@1883000 {
0161 compatible = "ns16550a";
0162 device_type = "serial";
0163 reg = <0x1883000 0x1000>;
0164 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0165 clock-frequency = <500000000>;
0166 reg-shift = <2>;
0167 reg-io-width = <4>;
0168 status = "disabled";
0169 };
0170
0171 uart1: serial@1884000 {
0172 compatible = "ns16550a";
0173 device_type = "serial";
0174 reg = <0x1884000 0x1000>;
0175 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0176 clock-frequency = <500000000>;
0177 reg-shift = <2>;
0178 reg-io-width = <4>;
0179 status = "disabled";
0180 };
0181
0182 uart2: serial@1885000 {
0183 compatible = "ns16550a";
0184 device_type = "serial";
0185 reg = <0x1885000 0x1000>;
0186 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0187 clock-frequency = <500000000>;
0188 reg-shift = <2>;
0189 reg-io-width = <4>;
0190 status = "disabled";
0191 };
0192
0193 uart3: serial@1886000 {
0194 compatible = "ns16550a";
0195 device_type = "serial";
0196 reg = <0x1886000 0x1000>;
0197 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0198 clock-frequency = <500000000>;
0199 reg-shift = <2>;
0200 reg-io-width = <4>;
0201 status = "disabled";
0202 };
0203
0204 timer0: timer@1890000 {
0205 compatible = "arm,sp804", "arm,primecell";
0206 reg = <0x1890000 0x1000>;
0207 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0208 clocks = <&sbclk>;
0209 };
0210
0211 timer1: timer@1891000 {
0212 compatible = "arm,sp804", "arm,primecell";
0213 reg = <0x1891000 0x1000>;
0214 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0215 clocks = <&sbclk>;
0216 status = "disabled";
0217 };
0218
0219 timer2: timer@1892000 {
0220 compatible = "arm,sp804", "arm,primecell";
0221 reg = <0x1892000 0x1000>;
0222 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0223 clocks = <&sbclk>;
0224 status = "disabled";
0225 };
0226
0227 timer3: timer@1893000 {
0228 compatible = "arm,sp804", "arm,primecell";
0229 reg = <0x1893000 0x1000>;
0230 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0231 clocks = <&sbclk>;
0232 status = "disabled";
0233 };
0234 };
0235 };
0236 };
