0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
0003
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/clock/sun50i-h6-ccu.h>
0006 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
0007 #include <dt-bindings/clock/sun6i-rtc.h>
0008 #include <dt-bindings/clock/sun8i-de2.h>
0009 #include <dt-bindings/clock/sun8i-tcon-top.h>
0010 #include <dt-bindings/reset/sun50i-h6-ccu.h>
0011 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
0012 #include <dt-bindings/reset/sun8i-de2.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014
0015 / {
0016 interrupt-parent = <&gic>;
0017 #address-cells = <1>;
0018 #size-cells = <1>;
0019
0020 cpus {
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023
0024 cpu0: cpu@0 {
0025 compatible = "arm,cortex-a53";
0026 device_type = "cpu";
0027 reg = <0>;
0028 enable-method = "psci";
0029 clocks = <&ccu CLK_CPUX>;
0030 clock-latency-ns = <244144>; /* 8 32k periods */
0031 #cooling-cells = <2>;
0032 };
0033
0034 cpu1: cpu@1 {
0035 compatible = "arm,cortex-a53";
0036 device_type = "cpu";
0037 reg = <1>;
0038 enable-method = "psci";
0039 clocks = <&ccu CLK_CPUX>;
0040 clock-latency-ns = <244144>; /* 8 32k periods */
0041 #cooling-cells = <2>;
0042 };
0043
0044 cpu2: cpu@2 {
0045 compatible = "arm,cortex-a53";
0046 device_type = "cpu";
0047 reg = <2>;
0048 enable-method = "psci";
0049 clocks = <&ccu CLK_CPUX>;
0050 clock-latency-ns = <244144>; /* 8 32k periods */
0051 #cooling-cells = <2>;
0052 };
0053
0054 cpu3: cpu@3 {
0055 compatible = "arm,cortex-a53";
0056 device_type = "cpu";
0057 reg = <3>;
0058 enable-method = "psci";
0059 clocks = <&ccu CLK_CPUX>;
0060 clock-latency-ns = <244144>; /* 8 32k periods */
0061 #cooling-cells = <2>;
0062 };
0063 };
0064
0065 de: display-engine {
0066 compatible = "allwinner,sun50i-h6-display-engine";
0067 allwinner,pipelines = <&mixer0>;
0068 status = "disabled";
0069 };
0070
0071 osc24M: osc24M_clk {
0072 #clock-cells = <0>;
0073 compatible = "fixed-clock";
0074 clock-frequency = <24000000>;
0075 clock-output-names = "osc24M";
0076 };
0077
0078 pmu {
0079 compatible = "arm,cortex-a53-pmu";
0080 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0081 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0084 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0085 };
0086
0087 psci {
0088 compatible = "arm,psci-0.2";
0089 method = "smc";
0090 };
0091
0092 timer {
0093 compatible = "arm,armv8-timer";
0094 arm,no-tick-in-suspend;
0095 interrupts = <GIC_PPI 13
0096 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0097 <GIC_PPI 14
0098 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0099 <GIC_PPI 11
0100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0101 <GIC_PPI 10
0102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0103 };
0104
0105 soc {
0106 compatible = "simple-bus";
0107 #address-cells = <1>;
0108 #size-cells = <1>;
0109 ranges;
0110
0111 bus@1000000 {
0112 compatible = "allwinner,sun50i-h6-de3",
0113 "allwinner,sun50i-a64-de2";
0114 reg = <0x1000000 0x400000>;
0115 allwinner,sram = <&de2_sram 1>;
0116 #address-cells = <1>;
0117 #size-cells = <1>;
0118 ranges = <0 0x1000000 0x400000>;
0119
0120 display_clocks: clock@0 {
0121 compatible = "allwinner,sun50i-h6-de3-clk";
0122 reg = <0x0 0x10000>;
0123 clocks = <&ccu CLK_BUS_DE>,
0124 <&ccu CLK_DE>;
0125 clock-names = "bus",
0126 "mod";
0127 resets = <&ccu RST_BUS_DE>;
0128 #clock-cells = <1>;
0129 #reset-cells = <1>;
0130 };
0131
0132 mixer0: mixer@100000 {
0133 compatible = "allwinner,sun50i-h6-de3-mixer-0";
0134 reg = <0x100000 0x100000>;
0135 clocks = <&display_clocks CLK_BUS_MIXER0>,
0136 <&display_clocks CLK_MIXER0>;
0137 clock-names = "bus",
0138 "mod";
0139 resets = <&display_clocks RST_MIXER0>;
0140 iommus = <&iommu 0>;
0141
0142 ports {
0143 #address-cells = <1>;
0144 #size-cells = <0>;
0145
0146 mixer0_out: port@1 {
0147 reg = <1>;
0148
0149 mixer0_out_tcon_top_mixer0: endpoint {
0150 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
0151 };
0152 };
0153 };
0154 };
0155 };
0156
0157 video-codec-g2@1c00000 {
0158 compatible = "allwinner,sun50i-h6-vpu-g2";
0159 reg = <0x01c00000 0x1000>;
0160 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0161 clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
0162 clock-names = "bus", "mod";
0163 resets = <&ccu RST_BUS_VP9>;
0164 };
0165
0166 video-codec@1c0e000 {
0167 compatible = "allwinner,sun50i-h6-video-engine";
0168 reg = <0x01c0e000 0x2000>;
0169 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
0170 <&ccu CLK_MBUS_VE>;
0171 clock-names = "ahb", "mod", "ram";
0172 resets = <&ccu RST_BUS_VE>;
0173 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0174 allwinner,sram = <&ve_sram 1>;
0175 iommus = <&iommu 3>;
0176 };
0177
0178 gpu: gpu@1800000 {
0179 compatible = "allwinner,sun50i-h6-mali",
0180 "arm,mali-t720";
0181 reg = <0x01800000 0x4000>;
0182 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0183 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0184 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0185 interrupt-names = "job", "mmu", "gpu";
0186 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
0187 clock-names = "core", "bus";
0188 resets = <&ccu RST_BUS_GPU>;
0189 status = "disabled";
0190 };
0191
0192 crypto: crypto@1904000 {
0193 compatible = "allwinner,sun50i-h6-crypto";
0194 reg = <0x01904000 0x1000>;
0195 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0196 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
0197 clock-names = "bus", "mod", "ram";
0198 resets = <&ccu RST_BUS_CE>;
0199 };
0200
0201 syscon: syscon@3000000 {
0202 compatible = "allwinner,sun50i-h6-system-control",
0203 "allwinner,sun50i-a64-system-control";
0204 reg = <0x03000000 0x1000>;
0205 #address-cells = <1>;
0206 #size-cells = <1>;
0207 ranges;
0208
0209 sram_c: sram@28000 {
0210 compatible = "mmio-sram";
0211 reg = <0x00028000 0x1e000>;
0212 #address-cells = <1>;
0213 #size-cells = <1>;
0214 ranges = <0 0x00028000 0x1e000>;
0215
0216 de2_sram: sram-section@0 {
0217 compatible = "allwinner,sun50i-h6-sram-c",
0218 "allwinner,sun50i-a64-sram-c";
0219 reg = <0x0000 0x1e000>;
0220 };
0221 };
0222
0223 sram_c1: sram@1a00000 {
0224 compatible = "mmio-sram";
0225 reg = <0x01a00000 0x200000>;
0226 #address-cells = <1>;
0227 #size-cells = <1>;
0228 ranges = <0 0x01a00000 0x200000>;
0229
0230 ve_sram: sram-section@0 {
0231 compatible = "allwinner,sun50i-h6-sram-c1",
0232 "allwinner,sun4i-a10-sram-c1";
0233 reg = <0x000000 0x200000>;
0234 };
0235 };
0236 };
0237
0238 ccu: clock@3001000 {
0239 compatible = "allwinner,sun50i-h6-ccu";
0240 reg = <0x03001000 0x1000>;
0241 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
0242 clock-names = "hosc", "losc", "iosc";
0243 #clock-cells = <1>;
0244 #reset-cells = <1>;
0245 };
0246
0247 dma: dma-controller@3002000 {
0248 compatible = "allwinner,sun50i-h6-dma";
0249 reg = <0x03002000 0x1000>;
0250 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0251 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
0252 clock-names = "bus", "mbus";
0253 dma-channels = <16>;
0254 dma-requests = <46>;
0255 resets = <&ccu RST_BUS_DMA>;
0256 #dma-cells = <1>;
0257 };
0258
0259 msgbox: mailbox@3003000 {
0260 compatible = "allwinner,sun50i-h6-msgbox",
0261 "allwinner,sun6i-a31-msgbox";
0262 reg = <0x03003000 0x1000>;
0263 clocks = <&ccu CLK_BUS_MSGBOX>;
0264 resets = <&ccu RST_BUS_MSGBOX>;
0265 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0266 #mbox-cells = <1>;
0267 };
0268
0269 sid: efuse@3006000 {
0270 compatible = "allwinner,sun50i-h6-sid";
0271 reg = <0x03006000 0x400>;
0272 #address-cells = <1>;
0273 #size-cells = <1>;
0274
0275 ths_calibration: thermal-sensor-calibration@14 {
0276 reg = <0x14 0x8>;
0277 };
0278
0279 cpu_speed_grade: cpu-speed-grade@1c {
0280 reg = <0x1c 0x4>;
0281 };
0282 };
0283
0284 timer@3009000 {
0285 compatible = "allwinner,sun50i-h6-timer",
0286 "allwinner,sun8i-a23-timer";
0287 reg = <0x03009000 0xa0>;
0288 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
0289 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0290 clocks = <&osc24M>;
0291 };
0292
0293 watchdog: watchdog@30090a0 {
0294 compatible = "allwinner,sun50i-h6-wdt",
0295 "allwinner,sun6i-a31-wdt";
0296 reg = <0x030090a0 0x20>;
0297 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0298 clocks = <&osc24M>;
0299 /* Broken on some H6 boards */
0300 status = "disabled";
0301 };
0302
0303 pwm: pwm@300a000 {
0304 compatible = "allwinner,sun50i-h6-pwm";
0305 reg = <0x0300a000 0x400>;
0306 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
0307 clock-names = "mod", "bus";
0308 resets = <&ccu RST_BUS_PWM>;
0309 #pwm-cells = <3>;
0310 status = "disabled";
0311 };
0312
0313 pio: pinctrl@300b000 {
0314 compatible = "allwinner,sun50i-h6-pinctrl";
0315 reg = <0x0300b000 0x400>;
0316 interrupt-parent = <&r_intc>;
0317 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0318 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0319 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0320 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0321 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
0322 clock-names = "apb", "hosc", "losc";
0323 gpio-controller;
0324 #gpio-cells = <3>;
0325 interrupt-controller;
0326 #interrupt-cells = <3>;
0327
0328 ext_rgmii_pins: rgmii-pins {
0329 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
0330 "PD5", "PD7", "PD8", "PD9", "PD10",
0331 "PD11", "PD12", "PD13", "PD19", "PD20";
0332 function = "emac";
0333 drive-strength = <40>;
0334 };
0335
0336 hdmi_pins: hdmi-pins {
0337 pins = "PH8", "PH9", "PH10";
0338 function = "hdmi";
0339 };
0340
0341 i2c0_pins: i2c0-pins {
0342 pins = "PD25", "PD26";
0343 function = "i2c0";
0344 };
0345
0346 i2c1_pins: i2c1-pins {
0347 pins = "PH5", "PH6";
0348 function = "i2c1";
0349 };
0350
0351 i2c2_pins: i2c2-pins {
0352 pins = "PD23", "PD24";
0353 function = "i2c2";
0354 };
0355
0356 mmc0_pins: mmc0-pins {
0357 pins = "PF0", "PF1", "PF2", "PF3",
0358 "PF4", "PF5";
0359 function = "mmc0";
0360 drive-strength = <30>;
0361 bias-pull-up;
0362 };
0363
0364 /omit-if-no-ref/
0365 mmc1_pins: mmc1-pins {
0366 pins = "PG0", "PG1", "PG2", "PG3",
0367 "PG4", "PG5";
0368 function = "mmc1";
0369 drive-strength = <30>;
0370 bias-pull-up;
0371 };
0372
0373 mmc2_pins: mmc2-pins {
0374 pins = "PC1", "PC4", "PC5", "PC6",
0375 "PC7", "PC8", "PC9", "PC10",
0376 "PC11", "PC12", "PC13", "PC14";
0377 function = "mmc2";
0378 drive-strength = <30>;
0379 bias-pull-up;
0380 };
0381
0382 /omit-if-no-ref/
0383 spi0_pins: spi0-pins {
0384 pins = "PC0", "PC2", "PC3";
0385 function = "spi0";
0386 };
0387
0388 /* pin shared with MMC2-CMD (eMMC) */
0389 /omit-if-no-ref/
0390 spi0_cs_pin: spi0-cs-pin {
0391 pins = "PC5";
0392 function = "spi0";
0393 };
0394
0395 /omit-if-no-ref/
0396 spi1_pins: spi1-pins {
0397 pins = "PH4", "PH5", "PH6";
0398 function = "spi1";
0399 };
0400
0401 /omit-if-no-ref/
0402 spi1_cs_pin: spi1-cs-pin {
0403 pins = "PH3";
0404 function = "spi1";
0405 };
0406
0407 spdif_tx_pin: spdif-tx-pin {
0408 pins = "PH7";
0409 function = "spdif";
0410 };
0411
0412 uart0_ph_pins: uart0-ph-pins {
0413 pins = "PH0", "PH1";
0414 function = "uart0";
0415 };
0416
0417 uart1_pins: uart1-pins {
0418 pins = "PG6", "PG7";
0419 function = "uart1";
0420 };
0421
0422 uart1_rts_cts_pins: uart1-rts-cts-pins {
0423 pins = "PG8", "PG9";
0424 function = "uart1";
0425 };
0426 };
0427
0428 gic: interrupt-controller@3021000 {
0429 compatible = "arm,gic-400";
0430 reg = <0x03021000 0x1000>,
0431 <0x03022000 0x2000>,
0432 <0x03024000 0x2000>,
0433 <0x03026000 0x2000>;
0434 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0435 interrupt-controller;
0436 #interrupt-cells = <3>;
0437 };
0438
0439 iommu: iommu@30f0000 {
0440 compatible = "allwinner,sun50i-h6-iommu";
0441 reg = <0x030f0000 0x10000>;
0442 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0443 clocks = <&ccu CLK_BUS_IOMMU>;
0444 resets = <&ccu RST_BUS_IOMMU>;
0445 #iommu-cells = <1>;
0446 };
0447
0448 mmc0: mmc@4020000 {
0449 compatible = "allwinner,sun50i-h6-mmc",
0450 "allwinner,sun50i-a64-mmc";
0451 reg = <0x04020000 0x1000>;
0452 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
0453 clock-names = "ahb", "mmc";
0454 resets = <&ccu RST_BUS_MMC0>;
0455 reset-names = "ahb";
0456 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0457 pinctrl-names = "default";
0458 pinctrl-0 = <&mmc0_pins>;
0459 max-frequency = <150000000>;
0460 status = "disabled";
0461 #address-cells = <1>;
0462 #size-cells = <0>;
0463 };
0464
0465 mmc1: mmc@4021000 {
0466 compatible = "allwinner,sun50i-h6-mmc",
0467 "allwinner,sun50i-a64-mmc";
0468 reg = <0x04021000 0x1000>;
0469 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
0470 clock-names = "ahb", "mmc";
0471 resets = <&ccu RST_BUS_MMC1>;
0472 reset-names = "ahb";
0473 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0474 pinctrl-names = "default";
0475 pinctrl-0 = <&mmc1_pins>;
0476 max-frequency = <150000000>;
0477 status = "disabled";
0478 #address-cells = <1>;
0479 #size-cells = <0>;
0480 };
0481
0482 mmc2: mmc@4022000 {
0483 compatible = "allwinner,sun50i-h6-emmc",
0484 "allwinner,sun50i-a64-emmc";
0485 reg = <0x04022000 0x1000>;
0486 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
0487 clock-names = "ahb", "mmc";
0488 resets = <&ccu RST_BUS_MMC2>;
0489 reset-names = "ahb";
0490 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0491 pinctrl-names = "default";
0492 pinctrl-0 = <&mmc2_pins>;
0493 max-frequency = <150000000>;
0494 status = "disabled";
0495 #address-cells = <1>;
0496 #size-cells = <0>;
0497 };
0498
0499 uart0: serial@5000000 {
0500 compatible = "snps,dw-apb-uart";
0501 reg = <0x05000000 0x400>;
0502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0503 reg-shift = <2>;
0504 reg-io-width = <4>;
0505 clocks = <&ccu CLK_BUS_UART0>;
0506 resets = <&ccu RST_BUS_UART0>;
0507 status = "disabled";
0508 };
0509
0510 uart1: serial@5000400 {
0511 compatible = "snps,dw-apb-uart";
0512 reg = <0x05000400 0x400>;
0513 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0514 reg-shift = <2>;
0515 reg-io-width = <4>;
0516 clocks = <&ccu CLK_BUS_UART1>;
0517 resets = <&ccu RST_BUS_UART1>;
0518 status = "disabled";
0519 };
0520
0521 uart2: serial@5000800 {
0522 compatible = "snps,dw-apb-uart";
0523 reg = <0x05000800 0x400>;
0524 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0525 reg-shift = <2>;
0526 reg-io-width = <4>;
0527 clocks = <&ccu CLK_BUS_UART2>;
0528 resets = <&ccu RST_BUS_UART2>;
0529 status = "disabled";
0530 };
0531
0532 uart3: serial@5000c00 {
0533 compatible = "snps,dw-apb-uart";
0534 reg = <0x05000c00 0x400>;
0535 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0536 reg-shift = <2>;
0537 reg-io-width = <4>;
0538 clocks = <&ccu CLK_BUS_UART3>;
0539 resets = <&ccu RST_BUS_UART3>;
0540 status = "disabled";
0541 };
0542
0543 i2c0: i2c@5002000 {
0544 compatible = "allwinner,sun50i-h6-i2c",
0545 "allwinner,sun6i-a31-i2c";
0546 reg = <0x05002000 0x400>;
0547 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0548 clocks = <&ccu CLK_BUS_I2C0>;
0549 resets = <&ccu RST_BUS_I2C0>;
0550 pinctrl-names = "default";
0551 pinctrl-0 = <&i2c0_pins>;
0552 status = "disabled";
0553 #address-cells = <1>;
0554 #size-cells = <0>;
0555 };
0556
0557 i2c1: i2c@5002400 {
0558 compatible = "allwinner,sun50i-h6-i2c",
0559 "allwinner,sun6i-a31-i2c";
0560 reg = <0x05002400 0x400>;
0561 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0562 clocks = <&ccu CLK_BUS_I2C1>;
0563 resets = <&ccu RST_BUS_I2C1>;
0564 pinctrl-names = "default";
0565 pinctrl-0 = <&i2c1_pins>;
0566 status = "disabled";
0567 #address-cells = <1>;
0568 #size-cells = <0>;
0569 };
0570
0571 i2c2: i2c@5002800 {
0572 compatible = "allwinner,sun50i-h6-i2c",
0573 "allwinner,sun6i-a31-i2c";
0574 reg = <0x05002800 0x400>;
0575 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0576 clocks = <&ccu CLK_BUS_I2C2>;
0577 resets = <&ccu RST_BUS_I2C2>;
0578 pinctrl-names = "default";
0579 pinctrl-0 = <&i2c2_pins>;
0580 status = "disabled";
0581 #address-cells = <1>;
0582 #size-cells = <0>;
0583 };
0584
0585 spi0: spi@5010000 {
0586 compatible = "allwinner,sun50i-h6-spi",
0587 "allwinner,sun8i-h3-spi";
0588 reg = <0x05010000 0x1000>;
0589 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0590 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
0591 clock-names = "ahb", "mod";
0592 dmas = <&dma 22>, <&dma 22>;
0593 dma-names = "rx", "tx";
0594 resets = <&ccu RST_BUS_SPI0>;
0595 status = "disabled";
0596 #address-cells = <1>;
0597 #size-cells = <0>;
0598 };
0599
0600 spi1: spi@5011000 {
0601 compatible = "allwinner,sun50i-h6-spi",
0602 "allwinner,sun8i-h3-spi";
0603 reg = <0x05011000 0x1000>;
0604 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0605 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
0606 clock-names = "ahb", "mod";
0607 dmas = <&dma 23>, <&dma 23>;
0608 dma-names = "rx", "tx";
0609 resets = <&ccu RST_BUS_SPI1>;
0610 status = "disabled";
0611 #address-cells = <1>;
0612 #size-cells = <0>;
0613 };
0614
0615 emac: ethernet@5020000 {
0616 compatible = "allwinner,sun50i-h6-emac",
0617 "allwinner,sun50i-a64-emac";
0618 syscon = <&syscon>;
0619 reg = <0x05020000 0x10000>;
0620 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0621 interrupt-names = "macirq";
0622 resets = <&ccu RST_BUS_EMAC>;
0623 reset-names = "stmmaceth";
0624 clocks = <&ccu CLK_BUS_EMAC>;
0625 clock-names = "stmmaceth";
0626 status = "disabled";
0627
0628 mdio: mdio {
0629 compatible = "snps,dwmac-mdio";
0630 #address-cells = <1>;
0631 #size-cells = <0>;
0632 };
0633 };
0634
0635 i2s1: i2s@5091000 {
0636 #sound-dai-cells = <0>;
0637 compatible = "allwinner,sun50i-h6-i2s";
0638 reg = <0x05091000 0x1000>;
0639 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0640 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
0641 clock-names = "apb", "mod";
0642 dmas = <&dma 4>, <&dma 4>;
0643 resets = <&ccu RST_BUS_I2S1>;
0644 dma-names = "rx", "tx";
0645 status = "disabled";
0646 };
0647
0648 spdif: spdif@5093000 {
0649 #sound-dai-cells = <0>;
0650 compatible = "allwinner,sun50i-h6-spdif";
0651 reg = <0x05093000 0x400>;
0652 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0653 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
0654 clock-names = "apb", "spdif";
0655 resets = <&ccu RST_BUS_SPDIF>;
0656 dmas = <&dma 2>;
0657 dma-names = "tx";
0658 pinctrl-names = "default";
0659 pinctrl-0 = <&spdif_tx_pin>;
0660 status = "disabled";
0661 };
0662
0663 usb2otg: usb@5100000 {
0664 compatible = "allwinner,sun50i-h6-musb",
0665 "allwinner,sun8i-a33-musb";
0666 reg = <0x05100000 0x0400>;
0667 clocks = <&ccu CLK_BUS_OTG>;
0668 resets = <&ccu RST_BUS_OTG>;
0669 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0670 interrupt-names = "mc";
0671 phys = <&usb2phy 0>;
0672 phy-names = "usb";
0673 extcon = <&usb2phy 0>;
0674 status = "disabled";
0675 };
0676
0677 usb2phy: phy@5100400 {
0678 compatible = "allwinner,sun50i-h6-usb-phy";
0679 reg = <0x05100400 0x24>,
0680 <0x05101800 0x4>,
0681 <0x05311800 0x4>;
0682 reg-names = "phy_ctrl",
0683 "pmu0",
0684 "pmu3";
0685 clocks = <&ccu CLK_USB_PHY0>,
0686 <&ccu CLK_USB_PHY3>;
0687 clock-names = "usb0_phy",
0688 "usb3_phy";
0689 resets = <&ccu RST_USB_PHY0>,
0690 <&ccu RST_USB_PHY3>;
0691 reset-names = "usb0_reset",
0692 "usb3_reset";
0693 status = "disabled";
0694 #phy-cells = <1>;
0695 };
0696
0697 ehci0: usb@5101000 {
0698 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
0699 reg = <0x05101000 0x100>;
0700 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0701 clocks = <&ccu CLK_BUS_OHCI0>,
0702 <&ccu CLK_BUS_EHCI0>,
0703 <&ccu CLK_USB_OHCI0>;
0704 resets = <&ccu RST_BUS_OHCI0>,
0705 <&ccu RST_BUS_EHCI0>;
0706 phys = <&usb2phy 0>;
0707 phy-names = "usb";
0708 status = "disabled";
0709 };
0710
0711 ohci0: usb@5101400 {
0712 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
0713 reg = <0x05101400 0x100>;
0714 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0715 clocks = <&ccu CLK_BUS_OHCI0>,
0716 <&ccu CLK_USB_OHCI0>;
0717 resets = <&ccu RST_BUS_OHCI0>;
0718 phys = <&usb2phy 0>;
0719 phy-names = "usb";
0720 status = "disabled";
0721 };
0722
0723 dwc3: usb@5200000 {
0724 compatible = "snps,dwc3";
0725 reg = <0x05200000 0x10000>;
0726 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0727 clocks = <&ccu CLK_BUS_XHCI>,
0728 <&ccu CLK_BUS_XHCI>,
0729 <&rtc CLK_OSC32K>;
0730 clock-names = "ref", "bus_early", "suspend";
0731 resets = <&ccu RST_BUS_XHCI>;
0732 /*
0733 * The datasheet of the chip doesn't declare the
0734 * peripheral function, and there's no boards known
0735 * to have a USB Type-B port routed to the port.
0736 * In addition, no one has tested the peripheral
0737 * function yet.
0738 * So set the dr_mode to "host" in the DTSI file.
0739 */
0740 dr_mode = "host";
0741 phys = <&usb3phy>;
0742 phy-names = "usb3-phy";
0743 status = "disabled";
0744 };
0745
0746 usb3phy: phy@5210000 {
0747 compatible = "allwinner,sun50i-h6-usb3-phy";
0748 reg = <0x5210000 0x10000>;
0749 clocks = <&ccu CLK_USB_PHY1>;
0750 resets = <&ccu RST_USB_PHY1>;
0751 #phy-cells = <0>;
0752 status = "disabled";
0753 };
0754
0755 ehci3: usb@5311000 {
0756 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
0757 reg = <0x05311000 0x100>;
0758 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0759 clocks = <&ccu CLK_BUS_OHCI3>,
0760 <&ccu CLK_BUS_EHCI3>,
0761 <&ccu CLK_USB_OHCI3>;
0762 resets = <&ccu RST_BUS_OHCI3>,
0763 <&ccu RST_BUS_EHCI3>;
0764 phys = <&usb2phy 3>;
0765 phy-names = "usb";
0766 status = "disabled";
0767 };
0768
0769 ohci3: usb@5311400 {
0770 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
0771 reg = <0x05311400 0x100>;
0772 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0773 clocks = <&ccu CLK_BUS_OHCI3>,
0774 <&ccu CLK_USB_OHCI3>;
0775 resets = <&ccu RST_BUS_OHCI3>;
0776 phys = <&usb2phy 3>;
0777 phy-names = "usb";
0778 status = "disabled";
0779 };
0780
0781 hdmi: hdmi@6000000 {
0782 compatible = "allwinner,sun50i-h6-dw-hdmi";
0783 reg = <0x06000000 0x10000>;
0784 reg-io-width = <1>;
0785 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0786 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
0787 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
0788 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
0789 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
0790 "hdcp-bus";
0791 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
0792 reset-names = "ctrl", "hdcp";
0793 phys = <&hdmi_phy>;
0794 phy-names = "phy";
0795 pinctrl-names = "default";
0796 pinctrl-0 = <&hdmi_pins>;
0797 status = "disabled";
0798
0799 ports {
0800 #address-cells = <1>;
0801 #size-cells = <0>;
0802
0803 hdmi_in: port@0 {
0804 reg = <0>;
0805
0806 hdmi_in_tcon_top: endpoint {
0807 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
0808 };
0809 };
0810
0811 hdmi_out: port@1 {
0812 reg = <1>;
0813 };
0814 };
0815 };
0816
0817 hdmi_phy: hdmi-phy@6010000 {
0818 compatible = "allwinner,sun50i-h6-hdmi-phy";
0819 reg = <0x06010000 0x10000>;
0820 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
0821 clock-names = "bus", "mod";
0822 resets = <&ccu RST_BUS_HDMI>;
0823 reset-names = "phy";
0824 #phy-cells = <0>;
0825 };
0826
0827 tcon_top: tcon-top@6510000 {
0828 compatible = "allwinner,sun50i-h6-tcon-top";
0829 reg = <0x06510000 0x1000>;
0830 clocks = <&ccu CLK_BUS_TCON_TOP>,
0831 <&ccu CLK_TCON_TV0>;
0832 clock-names = "bus",
0833 "tcon-tv0";
0834 clock-output-names = "tcon-top-tv0";
0835 resets = <&ccu RST_BUS_TCON_TOP>;
0836 #clock-cells = <1>;
0837
0838 ports {
0839 #address-cells = <1>;
0840 #size-cells = <0>;
0841
0842 tcon_top_mixer0_in: port@0 {
0843 #address-cells = <1>;
0844 #size-cells = <0>;
0845 reg = <0>;
0846
0847 tcon_top_mixer0_in_mixer0: endpoint@0 {
0848 reg = <0>;
0849 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
0850 };
0851 };
0852
0853 tcon_top_mixer0_out: port@1 {
0854 #address-cells = <1>;
0855 #size-cells = <0>;
0856 reg = <1>;
0857
0858 tcon_top_mixer0_out_tcon_tv: endpoint@2 {
0859 reg = <2>;
0860 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
0861 };
0862 };
0863
0864 tcon_top_hdmi_in: port@4 {
0865 #address-cells = <1>;
0866 #size-cells = <0>;
0867 reg = <4>;
0868
0869 tcon_top_hdmi_in_tcon_tv: endpoint@0 {
0870 reg = <0>;
0871 remote-endpoint = <&tcon_tv_out_tcon_top>;
0872 };
0873 };
0874
0875 tcon_top_hdmi_out: port@5 {
0876 reg = <5>;
0877
0878 tcon_top_hdmi_out_hdmi: endpoint {
0879 remote-endpoint = <&hdmi_in_tcon_top>;
0880 };
0881 };
0882 };
0883 };
0884
0885 tcon_tv: lcd-controller@6515000 {
0886 compatible = "allwinner,sun50i-h6-tcon-tv",
0887 "allwinner,sun8i-r40-tcon-tv";
0888 reg = <0x06515000 0x1000>;
0889 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0890 clocks = <&ccu CLK_BUS_TCON_TV0>,
0891 <&tcon_top CLK_TCON_TOP_TV0>;
0892 clock-names = "ahb",
0893 "tcon-ch1";
0894 resets = <&ccu RST_BUS_TCON_TV0>;
0895 reset-names = "lcd";
0896
0897 ports {
0898 #address-cells = <1>;
0899 #size-cells = <0>;
0900
0901 tcon_tv_in: port@0 {
0902 reg = <0>;
0903
0904 tcon_tv_in_tcon_top_mixer0: endpoint {
0905 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
0906 };
0907 };
0908
0909 tcon_tv_out: port@1 {
0910 #address-cells = <1>;
0911 #size-cells = <0>;
0912 reg = <1>;
0913
0914 tcon_tv_out_tcon_top: endpoint@1 {
0915 reg = <1>;
0916 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
0917 };
0918 };
0919 };
0920 };
0921
0922 rtc: rtc@7000000 {
0923 compatible = "allwinner,sun50i-h6-rtc";
0924 reg = <0x07000000 0x400>;
0925 interrupt-parent = <&r_intc>;
0926 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0927 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0928 clock-output-names = "osc32k", "osc32k-out", "iosc";
0929 #clock-cells = <1>;
0930 };
0931
0932 r_ccu: clock@7010000 {
0933 compatible = "allwinner,sun50i-h6-r-ccu";
0934 reg = <0x07010000 0x400>;
0935 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
0936 <&ccu CLK_PLL_PERIPH0>;
0937 clock-names = "hosc", "losc", "iosc", "pll-periph";
0938 #clock-cells = <1>;
0939 #reset-cells = <1>;
0940 };
0941
0942 r_watchdog: watchdog@7020400 {
0943 compatible = "allwinner,sun50i-h6-wdt",
0944 "allwinner,sun6i-a31-wdt";
0945 reg = <0x07020400 0x20>;
0946 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0947 clocks = <&osc24M>;
0948 };
0949
0950 r_intc: interrupt-controller@7021000 {
0951 compatible = "allwinner,sun50i-h6-r-intc";
0952 interrupt-controller;
0953 #interrupt-cells = <3>;
0954 reg = <0x07021000 0x400>;
0955 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0956 };
0957
0958 r_pio: pinctrl@7022000 {
0959 compatible = "allwinner,sun50i-h6-r-pinctrl";
0960 reg = <0x07022000 0x400>;
0961 interrupt-parent = <&r_intc>;
0962 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0963 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0964 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
0965 <&rtc CLK_OSC32K>;
0966 clock-names = "apb", "hosc", "losc";
0967 gpio-controller;
0968 #gpio-cells = <3>;
0969 interrupt-controller;
0970 #interrupt-cells = <3>;
0971
0972 r_i2c_pins: r-i2c-pins {
0973 pins = "PL0", "PL1";
0974 function = "s_i2c";
0975 };
0976
0977 r_ir_rx_pin: r-ir-rx-pin {
0978 pins = "PL9";
0979 function = "s_cir_rx";
0980 };
0981
0982 r_rsb_pins: r-rsb-pins {
0983 pins = "PL0", "PL1";
0984 function = "s_rsb";
0985 };
0986 };
0987
0988 r_ir: ir@7040000 {
0989 compatible = "allwinner,sun50i-h6-ir",
0990 "allwinner,sun6i-a31-ir";
0991 reg = <0x07040000 0x400>;
0992 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0993 clocks = <&r_ccu CLK_R_APB1_IR>,
0994 <&r_ccu CLK_IR>;
0995 clock-names = "apb", "ir";
0996 resets = <&r_ccu RST_R_APB1_IR>;
0997 pinctrl-names = "default";
0998 pinctrl-0 = <&r_ir_rx_pin>;
0999 status = "disabled";
1000 };
1001
1002 r_i2c: i2c@7081400 {
1003 compatible = "allwinner,sun50i-h6-i2c",
1004 "allwinner,sun6i-a31-i2c";
1005 reg = <0x07081400 0x400>;
1006 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&r_ccu CLK_R_APB2_I2C>;
1008 resets = <&r_ccu RST_R_APB2_I2C>;
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&r_i2c_pins>;
1011 status = "disabled";
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 };
1015
1016 r_rsb: rsb@7083000 {
1017 compatible = "allwinner,sun8i-a23-rsb";
1018 reg = <0x07083000 0x400>;
1019 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&r_ccu CLK_R_APB2_RSB>;
1021 clock-frequency = <3000000>;
1022 resets = <&r_ccu RST_R_APB2_RSB>;
1023 pinctrl-names = "default";
1024 pinctrl-0 = <&r_rsb_pins>;
1025 status = "disabled";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1028 };
1029
1030 ths: thermal-sensor@5070400 {
1031 compatible = "allwinner,sun50i-h6-ths";
1032 reg = <0x05070400 0x100>;
1033 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1034 clocks = <&ccu CLK_BUS_THS>;
1035 clock-names = "bus";
1036 resets = <&ccu RST_BUS_THS>;
1037 nvmem-cells = <&ths_calibration>;
1038 nvmem-cell-names = "calibration";
1039 #thermal-sensor-cells = <1>;
1040 };
1041 };
1042
1043 thermal-zones {
1044 cpu-thermal {
1045 polling-delay-passive = <0>;
1046 polling-delay = <0>;
1047 thermal-sensors = <&ths 0>;
1048
1049 trips {
1050 cpu_alert: cpu-alert {
1051 temperature = <85000>;
1052 hysteresis = <2000>;
1053 type = "passive";
1054 };
1055
1056 cpu-crit {
1057 temperature = <100000>;
1058 hysteresis = <0>;
1059 type = "critical";
1060 };
1061 };
1062
1063 cooling-maps {
1064 map0 {
1065 trip = <&cpu_alert>;
1066 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1067 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1068 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1069 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1070 };
1071 };
1072 };
1073
1074 gpu-thermal {
1075 polling-delay-passive = <0>;
1076 polling-delay = <0>;
1077 thermal-sensors = <&ths 1>;
1078 };
1079 };
1080 };
