Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/probes/kprobes/actions-thumb.c
0004  *
0005  * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
0006  */
0007 
0008 #include <linux/types.h>
0009 #include <linux/kernel.h>
0010 #include <linux/ptrace.h>
0011 #include <linux/kprobes.h>
0012 
0013 #include "../decode-thumb.h"
0014 #include "core.h"
0015 #include "checkers.h"
0016 
0017 /* These emulation encodings are functionally equivalent... */
0018 #define t32_emulate_rd8rn16rm0ra12_noflags \
0019         t32_emulate_rdlo12rdhi8rn16rm0_noflags
0020 
0021 /* t32 thumb actions */
0022 
0023 static void __kprobes
0024 t32_simulate_table_branch(probes_opcode_t insn,
0025         struct arch_probes_insn *asi, struct pt_regs *regs)
0026 {
0027     unsigned long pc = regs->ARM_pc;
0028     int rn = (insn >> 16) & 0xf;
0029     int rm = insn & 0xf;
0030 
0031     unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn];
0032     unsigned long rmv = regs->uregs[rm];
0033     unsigned int halfwords;
0034 
0035     if (insn & 0x10) /* TBH */
0036         halfwords = ((u16 *)rnv)[rmv];
0037     else /* TBB */
0038         halfwords = ((u8 *)rnv)[rmv];
0039 
0040     regs->ARM_pc = pc + 2 * halfwords;
0041 }
0042 
0043 static void __kprobes
0044 t32_simulate_mrs(probes_opcode_t insn,
0045         struct arch_probes_insn *asi, struct pt_regs *regs)
0046 {
0047     int rd = (insn >> 8) & 0xf;
0048     unsigned long mask = 0xf8ff03df; /* Mask out execution state */
0049     regs->uregs[rd] = regs->ARM_cpsr & mask;
0050 }
0051 
0052 static void __kprobes
0053 t32_simulate_cond_branch(probes_opcode_t insn,
0054         struct arch_probes_insn *asi, struct pt_regs *regs)
0055 {
0056     unsigned long pc = regs->ARM_pc;
0057 
0058     long offset = insn & 0x7ff;     /* imm11 */
0059     offset += (insn & 0x003f0000) >> 5; /* imm6 */
0060     offset += (insn & 0x00002000) << 4; /* J1 */
0061     offset += (insn & 0x00000800) << 7; /* J2 */
0062     offset -= (insn & 0x04000000) >> 7; /* Apply sign bit */
0063 
0064     regs->ARM_pc = pc + (offset * 2);
0065 }
0066 
0067 static enum probes_insn __kprobes
0068 t32_decode_cond_branch(probes_opcode_t insn, struct arch_probes_insn *asi,
0069         const struct decode_header *d)
0070 {
0071     int cc = (insn >> 22) & 0xf;
0072     asi->insn_check_cc = probes_condition_checks[cc];
0073     asi->insn_handler = t32_simulate_cond_branch;
0074     return INSN_GOOD_NO_SLOT;
0075 }
0076 
0077 static void __kprobes
0078 t32_simulate_branch(probes_opcode_t insn,
0079             struct arch_probes_insn *asi, struct pt_regs *regs)
0080 {
0081     unsigned long pc = regs->ARM_pc;
0082 
0083     long offset = insn & 0x7ff;     /* imm11 */
0084     offset += (insn & 0x03ff0000) >> 5; /* imm10 */
0085     offset += (insn & 0x00002000) << 9; /* J1 */
0086     offset += (insn & 0x00000800) << 10;    /* J2 */
0087     if (insn & 0x04000000)
0088         offset -= 0x00800000; /* Apply sign bit */
0089     else
0090         offset ^= 0x00600000; /* Invert J1 and J2 */
0091 
0092     if (insn & (1 << 14)) {
0093         /* BL or BLX */
0094         regs->ARM_lr = regs->ARM_pc | 1;
0095         if (!(insn & (1 << 12))) {
0096             /* BLX so switch to ARM mode */
0097             regs->ARM_cpsr &= ~PSR_T_BIT;
0098             pc &= ~3;
0099         }
0100     }
0101 
0102     regs->ARM_pc = pc + (offset * 2);
0103 }
0104 
0105 static void __kprobes
0106 t32_simulate_ldr_literal(probes_opcode_t insn,
0107         struct arch_probes_insn *asi, struct pt_regs *regs)
0108 {
0109     unsigned long addr = regs->ARM_pc & ~3;
0110     int rt = (insn >> 12) & 0xf;
0111     unsigned long rtv;
0112 
0113     long offset = insn & 0xfff;
0114     if (insn & 0x00800000)
0115         addr += offset;
0116     else
0117         addr -= offset;
0118 
0119     if (insn & 0x00400000) {
0120         /* LDR */
0121         rtv = *(unsigned long *)addr;
0122         if (rt == 15) {
0123             bx_write_pc(rtv, regs);
0124             return;
0125         }
0126     } else if (insn & 0x00200000) {
0127         /* LDRH */
0128         if (insn & 0x01000000)
0129             rtv = *(s16 *)addr;
0130         else
0131             rtv = *(u16 *)addr;
0132     } else {
0133         /* LDRB */
0134         if (insn & 0x01000000)
0135             rtv = *(s8 *)addr;
0136         else
0137             rtv = *(u8 *)addr;
0138     }
0139 
0140     regs->uregs[rt] = rtv;
0141 }
0142 
0143 static enum probes_insn __kprobes
0144 t32_decode_ldmstm(probes_opcode_t insn, struct arch_probes_insn *asi,
0145         const struct decode_header *d)
0146 {
0147     enum probes_insn ret = kprobe_decode_ldmstm(insn, asi, d);
0148 
0149     /* Fixup modified instruction to have halfwords in correct order...*/
0150     insn = __mem_to_opcode_arm(asi->insn[0]);
0151     ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn >> 16);
0152     ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0xffff);
0153 
0154     return ret;
0155 }
0156 
0157 static void __kprobes
0158 t32_emulate_ldrdstrd(probes_opcode_t insn,
0159         struct arch_probes_insn *asi, struct pt_regs *regs)
0160 {
0161     unsigned long pc = regs->ARM_pc & ~3;
0162     int rt1 = (insn >> 12) & 0xf;
0163     int rt2 = (insn >> 8) & 0xf;
0164     int rn = (insn >> 16) & 0xf;
0165 
0166     register unsigned long rt1v asm("r0") = regs->uregs[rt1];
0167     register unsigned long rt2v asm("r1") = regs->uregs[rt2];
0168     register unsigned long rnv asm("r2") = (rn == 15) ? pc
0169                               : regs->uregs[rn];
0170 
0171     __asm__ __volatile__ (
0172         "blx    %[fn]"
0173         : "=r" (rt1v), "=r" (rt2v), "=r" (rnv)
0174         : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (asi->insn_fn)
0175         : "lr", "memory", "cc"
0176     );
0177 
0178     if (rn != 15)
0179         regs->uregs[rn] = rnv; /* Writeback base register */
0180     regs->uregs[rt1] = rt1v;
0181     regs->uregs[rt2] = rt2v;
0182 }
0183 
0184 static void __kprobes
0185 t32_emulate_ldrstr(probes_opcode_t insn,
0186         struct arch_probes_insn *asi, struct pt_regs *regs)
0187 {
0188     int rt = (insn >> 12) & 0xf;
0189     int rn = (insn >> 16) & 0xf;
0190     int rm = insn & 0xf;
0191 
0192     register unsigned long rtv asm("r0") = regs->uregs[rt];
0193     register unsigned long rnv asm("r2") = regs->uregs[rn];
0194     register unsigned long rmv asm("r3") = regs->uregs[rm];
0195 
0196     __asm__ __volatile__ (
0197         "blx    %[fn]"
0198         : "=r" (rtv), "=r" (rnv)
0199         : "0" (rtv), "1" (rnv), "r" (rmv), [fn] "r" (asi->insn_fn)
0200         : "lr", "memory", "cc"
0201     );
0202 
0203     regs->uregs[rn] = rnv; /* Writeback base register */
0204     if (rt == 15) /* Can't be true for a STR as they aren't allowed */
0205         bx_write_pc(rtv, regs);
0206     else
0207         regs->uregs[rt] = rtv;
0208 }
0209 
0210 static void __kprobes
0211 t32_emulate_rd8rn16rm0_rwflags(probes_opcode_t insn,
0212         struct arch_probes_insn *asi, struct pt_regs *regs)
0213 {
0214     int rd = (insn >> 8) & 0xf;
0215     int rn = (insn >> 16) & 0xf;
0216     int rm = insn & 0xf;
0217 
0218     register unsigned long rdv asm("r1") = regs->uregs[rd];
0219     register unsigned long rnv asm("r2") = regs->uregs[rn];
0220     register unsigned long rmv asm("r3") = regs->uregs[rm];
0221     unsigned long cpsr = regs->ARM_cpsr;
0222 
0223     __asm__ __volatile__ (
0224         "msr    cpsr_fs, %[cpsr]    \n\t"
0225         "blx    %[fn]           \n\t"
0226         "mrs    %[cpsr], cpsr       \n\t"
0227         : "=r" (rdv), [cpsr] "=r" (cpsr)
0228         : "0" (rdv), "r" (rnv), "r" (rmv),
0229           "1" (cpsr), [fn] "r" (asi->insn_fn)
0230         : "lr", "memory", "cc"
0231     );
0232 
0233     regs->uregs[rd] = rdv;
0234     regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
0235 }
0236 
0237 static void __kprobes
0238 t32_emulate_rd8pc16_noflags(probes_opcode_t insn,
0239         struct arch_probes_insn *asi, struct pt_regs *regs)
0240 {
0241     unsigned long pc = regs->ARM_pc;
0242     int rd = (insn >> 8) & 0xf;
0243 
0244     register unsigned long rdv asm("r1") = regs->uregs[rd];
0245     register unsigned long rnv asm("r2") = pc & ~3;
0246 
0247     __asm__ __volatile__ (
0248         "blx    %[fn]"
0249         : "=r" (rdv)
0250         : "0" (rdv), "r" (rnv), [fn] "r" (asi->insn_fn)
0251         : "lr", "memory", "cc"
0252     );
0253 
0254     regs->uregs[rd] = rdv;
0255 }
0256 
0257 static void __kprobes
0258 t32_emulate_rd8rn16_noflags(probes_opcode_t insn,
0259         struct arch_probes_insn *asi, struct pt_regs *regs)
0260 {
0261     int rd = (insn >> 8) & 0xf;
0262     int rn = (insn >> 16) & 0xf;
0263 
0264     register unsigned long rdv asm("r1") = regs->uregs[rd];
0265     register unsigned long rnv asm("r2") = regs->uregs[rn];
0266 
0267     __asm__ __volatile__ (
0268         "blx    %[fn]"
0269         : "=r" (rdv)
0270         : "0" (rdv), "r" (rnv), [fn] "r" (asi->insn_fn)
0271         : "lr", "memory", "cc"
0272     );
0273 
0274     regs->uregs[rd] = rdv;
0275 }
0276 
0277 static void __kprobes
0278 t32_emulate_rdlo12rdhi8rn16rm0_noflags(probes_opcode_t insn,
0279         struct arch_probes_insn *asi,
0280         struct pt_regs *regs)
0281 {
0282     int rdlo = (insn >> 12) & 0xf;
0283     int rdhi = (insn >> 8) & 0xf;
0284     int rn = (insn >> 16) & 0xf;
0285     int rm = insn & 0xf;
0286 
0287     register unsigned long rdlov asm("r0") = regs->uregs[rdlo];
0288     register unsigned long rdhiv asm("r1") = regs->uregs[rdhi];
0289     register unsigned long rnv asm("r2") = regs->uregs[rn];
0290     register unsigned long rmv asm("r3") = regs->uregs[rm];
0291 
0292     __asm__ __volatile__ (
0293         "blx    %[fn]"
0294         : "=r" (rdlov), "=r" (rdhiv)
0295         : "0" (rdlov), "1" (rdhiv), "r" (rnv), "r" (rmv),
0296           [fn] "r" (asi->insn_fn)
0297         : "lr", "memory", "cc"
0298     );
0299 
0300     regs->uregs[rdlo] = rdlov;
0301     regs->uregs[rdhi] = rdhiv;
0302 }
0303 /* t16 thumb actions */
0304 
0305 static void __kprobes
0306 t16_simulate_bxblx(probes_opcode_t insn,
0307         struct arch_probes_insn *asi, struct pt_regs *regs)
0308 {
0309     unsigned long pc = regs->ARM_pc + 2;
0310     int rm = (insn >> 3) & 0xf;
0311     unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
0312 
0313     if (insn & (1 << 7)) /* BLX ? */
0314         regs->ARM_lr = regs->ARM_pc | 1;
0315 
0316     bx_write_pc(rmv, regs);
0317 }
0318 
0319 static void __kprobes
0320 t16_simulate_ldr_literal(probes_opcode_t insn,
0321         struct arch_probes_insn *asi, struct pt_regs *regs)
0322 {
0323     unsigned long *base = (unsigned long *)((regs->ARM_pc + 2) & ~3);
0324     long index = insn & 0xff;
0325     int rt = (insn >> 8) & 0x7;
0326     regs->uregs[rt] = base[index];
0327 }
0328 
0329 static void __kprobes
0330 t16_simulate_ldrstr_sp_relative(probes_opcode_t insn,
0331         struct arch_probes_insn *asi, struct pt_regs *regs)
0332 {
0333     unsigned long* base = (unsigned long *)regs->ARM_sp;
0334     long index = insn & 0xff;
0335     int rt = (insn >> 8) & 0x7;
0336     if (insn & 0x800) /* LDR */
0337         regs->uregs[rt] = base[index];
0338     else /* STR */
0339         base[index] = regs->uregs[rt];
0340 }
0341 
0342 static void __kprobes
0343 t16_simulate_reladr(probes_opcode_t insn,
0344         struct arch_probes_insn *asi, struct pt_regs *regs)
0345 {
0346     unsigned long base = (insn & 0x800) ? regs->ARM_sp
0347                         : ((regs->ARM_pc + 2) & ~3);
0348     long offset = insn & 0xff;
0349     int rt = (insn >> 8) & 0x7;
0350     regs->uregs[rt] = base + offset * 4;
0351 }
0352 
0353 static void __kprobes
0354 t16_simulate_add_sp_imm(probes_opcode_t insn,
0355         struct arch_probes_insn *asi, struct pt_regs *regs)
0356 {
0357     long imm = insn & 0x7f;
0358     if (insn & 0x80) /* SUB */
0359         regs->ARM_sp -= imm * 4;
0360     else /* ADD */
0361         regs->ARM_sp += imm * 4;
0362 }
0363 
0364 static void __kprobes
0365 t16_simulate_cbz(probes_opcode_t insn,
0366         struct arch_probes_insn *asi, struct pt_regs *regs)
0367 {
0368     int rn = insn & 0x7;
0369     probes_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
0370     if (nonzero & 0x800) {
0371         long i = insn & 0x200;
0372         long imm5 = insn & 0xf8;
0373         unsigned long pc = regs->ARM_pc + 2;
0374         regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
0375     }
0376 }
0377 
0378 static void __kprobes
0379 t16_simulate_it(probes_opcode_t insn,
0380         struct arch_probes_insn *asi, struct pt_regs *regs)
0381 {
0382     /*
0383      * The 8 IT state bits are split into two parts in CPSR:
0384      *  ITSTATE<1:0> are in CPSR<26:25>
0385      *  ITSTATE<7:2> are in CPSR<15:10>
0386      * The new IT state is in the lower byte of insn.
0387      */
0388     unsigned long cpsr = regs->ARM_cpsr;
0389     cpsr &= ~PSR_IT_MASK;
0390     cpsr |= (insn & 0xfc) << 8;
0391     cpsr |= (insn & 0x03) << 25;
0392     regs->ARM_cpsr = cpsr;
0393 }
0394 
0395 static void __kprobes
0396 t16_singlestep_it(probes_opcode_t insn,
0397           struct arch_probes_insn *asi, struct pt_regs *regs)
0398 {
0399     regs->ARM_pc += 2;
0400     t16_simulate_it(insn, asi, regs);
0401 }
0402 
0403 static enum probes_insn __kprobes
0404 t16_decode_it(probes_opcode_t insn, struct arch_probes_insn *asi,
0405         const struct decode_header *d)
0406 {
0407     asi->insn_singlestep = t16_singlestep_it;
0408     return INSN_GOOD_NO_SLOT;
0409 }
0410 
0411 static void __kprobes
0412 t16_simulate_cond_branch(probes_opcode_t insn,
0413         struct arch_probes_insn *asi, struct pt_regs *regs)
0414 {
0415     unsigned long pc = regs->ARM_pc + 2;
0416     long offset = insn & 0x7f;
0417     offset -= insn & 0x80; /* Apply sign bit */
0418     regs->ARM_pc = pc + (offset * 2);
0419 }
0420 
0421 static enum probes_insn __kprobes
0422 t16_decode_cond_branch(probes_opcode_t insn, struct arch_probes_insn *asi,
0423         const struct decode_header *d)
0424 {
0425     int cc = (insn >> 8) & 0xf;
0426     asi->insn_check_cc = probes_condition_checks[cc];
0427     asi->insn_handler = t16_simulate_cond_branch;
0428     return INSN_GOOD_NO_SLOT;
0429 }
0430 
0431 static void __kprobes
0432 t16_simulate_branch(probes_opcode_t insn,
0433            struct arch_probes_insn *asi, struct pt_regs *regs)
0434 {
0435     unsigned long pc = regs->ARM_pc + 2;
0436     long offset = insn & 0x3ff;
0437     offset -= insn & 0x400; /* Apply sign bit */
0438     regs->ARM_pc = pc + (offset * 2);
0439 }
0440 
0441 static unsigned long __kprobes
0442 t16_emulate_loregs(probes_opcode_t insn,
0443            struct arch_probes_insn *asi, struct pt_regs *regs)
0444 {
0445     unsigned long oldcpsr = regs->ARM_cpsr;
0446     unsigned long newcpsr;
0447 
0448     __asm__ __volatile__ (
0449         "msr    cpsr_fs, %[oldcpsr] \n\t"
0450         "mov    r11, r7         \n\t"
0451         "ldmia  %[regs], {r0-r7}    \n\t"
0452         "blx    %[fn]           \n\t"
0453         "stmia  %[regs], {r0-r7}    \n\t"
0454         "mov    r7, r11         \n\t"
0455         "mrs    %[newcpsr], cpsr    \n\t"
0456         : [newcpsr] "=r" (newcpsr)
0457         : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
0458           [fn] "r" (asi->insn_fn)
0459         : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r11",
0460           "lr", "memory", "cc"
0461         );
0462 
0463     return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
0464 }
0465 
0466 static void __kprobes
0467 t16_emulate_loregs_rwflags(probes_opcode_t insn,
0468         struct arch_probes_insn *asi, struct pt_regs *regs)
0469 {
0470     regs->ARM_cpsr = t16_emulate_loregs(insn, asi, regs);
0471 }
0472 
0473 static void __kprobes
0474 t16_emulate_loregs_noitrwflags(probes_opcode_t insn,
0475         struct arch_probes_insn *asi, struct pt_regs *regs)
0476 {
0477     unsigned long cpsr = t16_emulate_loregs(insn, asi, regs);
0478     if (!in_it_block(cpsr))
0479         regs->ARM_cpsr = cpsr;
0480 }
0481 
0482 static void __kprobes
0483 t16_emulate_hiregs(probes_opcode_t insn,
0484         struct arch_probes_insn *asi, struct pt_regs *regs)
0485 {
0486     unsigned long pc = regs->ARM_pc + 2;
0487     int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
0488     int rm = (insn >> 3) & 0xf;
0489 
0490     register unsigned long rdnv asm("r1");
0491     register unsigned long rmv asm("r0");
0492     unsigned long cpsr = regs->ARM_cpsr;
0493 
0494     rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
0495     rmv = (rm == 15) ? pc : regs->uregs[rm];
0496 
0497     __asm__ __volatile__ (
0498         "msr    cpsr_fs, %[cpsr]    \n\t"
0499         "blx    %[fn]           \n\t"
0500         "mrs    %[cpsr], cpsr       \n\t"
0501         : "=r" (rdnv), [cpsr] "=r" (cpsr)
0502         : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (asi->insn_fn)
0503         : "lr", "memory", "cc"
0504     );
0505 
0506     if (rdn == 15)
0507         rdnv &= ~1;
0508 
0509     regs->uregs[rdn] = rdnv;
0510     regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
0511 }
0512 
0513 static enum probes_insn __kprobes
0514 t16_decode_hiregs(probes_opcode_t insn, struct arch_probes_insn *asi,
0515         const struct decode_header *d)
0516 {
0517     insn &= ~0x00ff;
0518     insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
0519     ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(insn);
0520     asi->insn_handler = t16_emulate_hiregs;
0521     return INSN_GOOD;
0522 }
0523 
0524 static void __kprobes
0525 t16_emulate_push(probes_opcode_t insn,
0526         struct arch_probes_insn *asi, struct pt_regs *regs)
0527 {
0528     __asm__ __volatile__ (
0529         "mov    r11, r7         \n\t"
0530         "ldr    r9, [%[regs], #13*4]    \n\t"
0531         "ldr    r8, [%[regs], #14*4]    \n\t"
0532         "ldmia  %[regs], {r0-r7}    \n\t"
0533         "blx    %[fn]           \n\t"
0534         "str    r9, [%[regs], #13*4]    \n\t"
0535         "mov    r7, r11         \n\t"
0536         :
0537         : [regs] "r" (regs), [fn] "r" (asi->insn_fn)
0538         : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r11",
0539           "lr", "memory", "cc"
0540         );
0541 }
0542 
0543 static enum probes_insn __kprobes
0544 t16_decode_push(probes_opcode_t insn, struct arch_probes_insn *asi,
0545         const struct decode_header *d)
0546 {
0547     /*
0548      * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
0549      * and call it with R9=SP and LR in the register list represented
0550      * by R8.
0551      */
0552     /* 1st half STMDB R9!,{} */
0553     ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe929);
0554     /* 2nd half (register list) */
0555     ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff);
0556     asi->insn_handler = t16_emulate_push;
0557     return INSN_GOOD;
0558 }
0559 
0560 static void __kprobes
0561 t16_emulate_pop_nopc(probes_opcode_t insn,
0562         struct arch_probes_insn *asi, struct pt_regs *regs)
0563 {
0564     __asm__ __volatile__ (
0565         "mov    r11, r7         \n\t"
0566         "ldr    r9, [%[regs], #13*4]    \n\t"
0567         "ldmia  %[regs], {r0-r7}    \n\t"
0568         "blx    %[fn]           \n\t"
0569         "stmia  %[regs], {r0-r7}    \n\t"
0570         "str    r9, [%[regs], #13*4]    \n\t"
0571         "mov    r7, r11         \n\t"
0572         :
0573         : [regs] "r" (regs), [fn] "r" (asi->insn_fn)
0574         : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r9", "r11",
0575           "lr", "memory", "cc"
0576         );
0577 }
0578 
0579 static void __kprobes
0580 t16_emulate_pop_pc(probes_opcode_t insn,
0581         struct arch_probes_insn *asi, struct pt_regs *regs)
0582 {
0583     register unsigned long pc asm("r8");
0584 
0585     __asm__ __volatile__ (
0586         "mov    r11, r7         \n\t"
0587         "ldr    r9, [%[regs], #13*4]    \n\t"
0588         "ldmia  %[regs], {r0-r7}    \n\t"
0589         "blx    %[fn]           \n\t"
0590         "stmia  %[regs], {r0-r7}    \n\t"
0591         "str    r9, [%[regs], #13*4]    \n\t"
0592         "mov    r7, r11         \n\t"
0593         : "=r" (pc)
0594         : [regs] "r" (regs), [fn] "r" (asi->insn_fn)
0595         : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r9", "r11",
0596           "lr", "memory", "cc"
0597         );
0598 
0599     bx_write_pc(pc, regs);
0600 }
0601 
0602 static enum probes_insn __kprobes
0603 t16_decode_pop(probes_opcode_t insn, struct arch_probes_insn *asi,
0604         const struct decode_header *d)
0605 {
0606     /*
0607      * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
0608      * and call it with R9=SP and PC in the register list represented
0609      * by R8.
0610      */
0611     /* 1st half LDMIA R9!,{} */
0612     ((u16 *)asi->insn)[0] = __opcode_to_mem_thumb16(0xe8b9);
0613     /* 2nd half (register list) */
0614     ((u16 *)asi->insn)[1] = __opcode_to_mem_thumb16(insn & 0x1ff);
0615     asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
0616                      : t16_emulate_pop_nopc;
0617     return INSN_GOOD;
0618 }
0619 
0620 const union decode_action kprobes_t16_actions[NUM_PROBES_T16_ACTIONS] = {
0621     [PROBES_T16_ADD_SP] = {.handler = t16_simulate_add_sp_imm},
0622     [PROBES_T16_CBZ] = {.handler = t16_simulate_cbz},
0623     [PROBES_T16_SIGN_EXTEND] = {.handler = t16_emulate_loregs_rwflags},
0624     [PROBES_T16_PUSH] = {.decoder = t16_decode_push},
0625     [PROBES_T16_POP] = {.decoder = t16_decode_pop},
0626     [PROBES_T16_SEV] = {.handler = probes_emulate_none},
0627     [PROBES_T16_WFE] = {.handler = probes_simulate_nop},
0628     [PROBES_T16_IT] = {.decoder = t16_decode_it},
0629     [PROBES_T16_CMP] = {.handler = t16_emulate_loregs_rwflags},
0630     [PROBES_T16_ADDSUB] = {.handler = t16_emulate_loregs_noitrwflags},
0631     [PROBES_T16_LOGICAL] = {.handler = t16_emulate_loregs_noitrwflags},
0632     [PROBES_T16_LDR_LIT] = {.handler = t16_simulate_ldr_literal},
0633     [PROBES_T16_BLX] = {.handler = t16_simulate_bxblx},
0634     [PROBES_T16_HIREGOPS] = {.decoder = t16_decode_hiregs},
0635     [PROBES_T16_LDRHSTRH] = {.handler = t16_emulate_loregs_rwflags},
0636     [PROBES_T16_LDRSTR] = {.handler = t16_simulate_ldrstr_sp_relative},
0637     [PROBES_T16_ADR] = {.handler = t16_simulate_reladr},
0638     [PROBES_T16_LDMSTM] = {.handler = t16_emulate_loregs_rwflags},
0639     [PROBES_T16_BRANCH_COND] = {.decoder = t16_decode_cond_branch},
0640     [PROBES_T16_BRANCH] = {.handler = t16_simulate_branch},
0641 };
0642 
0643 const union decode_action kprobes_t32_actions[NUM_PROBES_T32_ACTIONS] = {
0644     [PROBES_T32_LDMSTM] = {.decoder = t32_decode_ldmstm},
0645     [PROBES_T32_LDRDSTRD] = {.handler = t32_emulate_ldrdstrd},
0646     [PROBES_T32_TABLE_BRANCH] = {.handler = t32_simulate_table_branch},
0647     [PROBES_T32_TST] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0648     [PROBES_T32_MOV] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0649     [PROBES_T32_ADDSUB] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0650     [PROBES_T32_LOGICAL] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0651     [PROBES_T32_CMP] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0652     [PROBES_T32_ADDWSUBW_PC] = {.handler = t32_emulate_rd8pc16_noflags,},
0653     [PROBES_T32_ADDWSUBW] = {.handler = t32_emulate_rd8rn16_noflags},
0654     [PROBES_T32_MOVW] = {.handler = t32_emulate_rd8rn16_noflags},
0655     [PROBES_T32_SAT] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0656     [PROBES_T32_BITFIELD] = {.handler = t32_emulate_rd8rn16_noflags},
0657     [PROBES_T32_SEV] = {.handler = probes_emulate_none},
0658     [PROBES_T32_WFE] = {.handler = probes_simulate_nop},
0659     [PROBES_T32_MRS] = {.handler = t32_simulate_mrs},
0660     [PROBES_T32_BRANCH_COND] = {.decoder = t32_decode_cond_branch},
0661     [PROBES_T32_BRANCH] = {.handler = t32_simulate_branch},
0662     [PROBES_T32_PLDI] = {.handler = probes_simulate_nop},
0663     [PROBES_T32_LDR_LIT] = {.handler = t32_simulate_ldr_literal},
0664     [PROBES_T32_LDRSTR] = {.handler = t32_emulate_ldrstr},
0665     [PROBES_T32_SIGN_EXTEND] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0666     [PROBES_T32_MEDIA] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0667     [PROBES_T32_REVERSE] = {.handler = t32_emulate_rd8rn16_noflags},
0668     [PROBES_T32_MUL_ADD] = {.handler = t32_emulate_rd8rn16rm0_rwflags},
0669     [PROBES_T32_MUL_ADD2] = {.handler = t32_emulate_rd8rn16rm0ra12_noflags},
0670     [PROBES_T32_MUL_ADD_LONG] = {
0671         .handler = t32_emulate_rdlo12rdhi8rn16rm0_noflags},
0672 };
0673 
0674 const struct decode_checker *kprobes_t32_checkers[] = {t32_stack_checker, NULL};
0675 const struct decode_checker *kprobes_t16_checkers[] = {t16_stack_checker, NULL};
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!