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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * arch/arm/probes/decode-arm.c
0005  *
0006  * Some code moved here from arch/arm/kernel/kprobes-arm.c
0007  *
0008  * Copyright (C) 2006, 2007 Motorola Inc.
0009  */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/stddef.h>
0014 #include <linux/ptrace.h>
0015 
0016 #include "decode.h"
0017 #include "decode-arm.h"
0018 
0019 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
0020 
0021 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
0022 
0023 /*
0024  * To avoid the complications of mimicing single-stepping on a
0025  * processor without a Next-PC or a single-step mode, and to
0026  * avoid having to deal with the side-effects of boosting, we
0027  * simulate or emulate (almost) all ARM instructions.
0028  *
0029  * "Simulation" is where the instruction's behavior is duplicated in
0030  * C code.  "Emulation" is where the original instruction is rewritten
0031  * and executed, often by altering its registers.
0032  *
0033  * By having all behavior of the kprobe'd instruction completed before
0034  * returning from the kprobe_handler(), all locks (scheduler and
0035  * interrupt) can safely be released.  There is no need for secondary
0036  * breakpoints, no race with MP or preemptable kernels, nor having to
0037  * clean up resources counts at a later time impacting overall system
0038  * performance.  By rewriting the instruction, only the minimum registers
0039  * need to be loaded and saved back optimizing performance.
0040  *
0041  * Calling the insnslot_*_rwflags version of a function doesn't hurt
0042  * anything even when the CPSR flags aren't updated by the
0043  * instruction.  It's just a little slower in return for saving
0044  * a little space by not having a duplicate function that doesn't
0045  * update the flags.  (The same optimization can be said for
0046  * instructions that do or don't perform register writeback)
0047  * Also, instructions can either read the flags, only write the
0048  * flags, or read and write the flags.  To save combinations
0049  * rather than for sheer performance, flag functions just assume
0050  * read and write of flags.
0051  */
0052 
0053 void __kprobes simulate_bbl(probes_opcode_t insn,
0054         struct arch_probes_insn *asi, struct pt_regs *regs)
0055 {
0056     long iaddr = (long) regs->ARM_pc - 4;
0057     int disp  = branch_displacement(insn);
0058 
0059     if (insn & (1 << 24))
0060         regs->ARM_lr = iaddr + 4;
0061 
0062     regs->ARM_pc = iaddr + 8 + disp;
0063 }
0064 
0065 void __kprobes simulate_blx1(probes_opcode_t insn,
0066         struct arch_probes_insn *asi, struct pt_regs *regs)
0067 {
0068     long iaddr = (long) regs->ARM_pc - 4;
0069     int disp = branch_displacement(insn);
0070 
0071     regs->ARM_lr = iaddr + 4;
0072     regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
0073     regs->ARM_cpsr |= PSR_T_BIT;
0074 }
0075 
0076 void __kprobes simulate_blx2bx(probes_opcode_t insn,
0077         struct arch_probes_insn *asi, struct pt_regs *regs)
0078 {
0079     int rm = insn & 0xf;
0080     long rmv = regs->uregs[rm];
0081 
0082     if (insn & (1 << 5))
0083         regs->ARM_lr = (long) regs->ARM_pc;
0084 
0085     regs->ARM_pc = rmv & ~0x1;
0086     regs->ARM_cpsr &= ~PSR_T_BIT;
0087     if (rmv & 0x1)
0088         regs->ARM_cpsr |= PSR_T_BIT;
0089 }
0090 
0091 void __kprobes simulate_mrs(probes_opcode_t insn,
0092         struct arch_probes_insn *asi, struct pt_regs *regs)
0093 {
0094     int rd = (insn >> 12) & 0xf;
0095     unsigned long mask = 0xf8ff03df; /* Mask out execution state */
0096     regs->uregs[rd] = regs->ARM_cpsr & mask;
0097 }
0098 
0099 void __kprobes simulate_mov_ipsp(probes_opcode_t insn,
0100         struct arch_probes_insn *asi, struct pt_regs *regs)
0101 {
0102     regs->uregs[12] = regs->uregs[13];
0103 }
0104 
0105 /*
0106  * For the instruction masking and comparisons in all the "space_*"
0107  * functions below, Do _not_ rearrange the order of tests unless
0108  * you're very, very sure of what you are doing.  For the sake of
0109  * efficiency, the masks for some tests sometimes assume other test
0110  * have been done prior to them so the number of patterns to test
0111  * for an instruction set can be as broad as possible to reduce the
0112  * number of tests needed.
0113  */
0114 
0115 static const union decode_item arm_1111_table[] = {
0116     /* Unconditional instructions                   */
0117 
0118     /* memory hint      1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */
0119     /* PLDI (immediate) 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */
0120     /* PLDW (immediate) 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */
0121     /* PLD (immediate)  1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */
0122     DECODE_SIMULATE (0xfe300000, 0xf4100000, PROBES_PRELOAD_IMM),
0123 
0124     /* memory hint      1111 0110 x001 xxxx xxxx xxxx xxx0 xxxx */
0125     /* PLDI (register)  1111 0110 x101 xxxx xxxx xxxx xxx0 xxxx */
0126     /* PLDW (register)  1111 0111 x001 xxxx xxxx xxxx xxx0 xxxx */
0127     /* PLD (register)   1111 0111 x101 xxxx xxxx xxxx xxx0 xxxx */
0128     DECODE_SIMULATE (0xfe300010, 0xf6100000, PROBES_PRELOAD_REG),
0129 
0130     /* BLX (immediate)  1111 101x xxxx xxxx xxxx xxxx xxxx xxxx */
0131     DECODE_SIMULATE (0xfe000000, 0xfa000000, PROBES_BRANCH_IMM),
0132 
0133     /* CPS          1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */
0134     /* SETEND       1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
0135     /* SRS          1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
0136     /* RFE          1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
0137 
0138     /* Coprocessor instructions... */
0139     /* MCRR2        1111 1100 0100 xxxx xxxx xxxx xxxx xxxx */
0140     /* MRRC2        1111 1100 0101 xxxx xxxx xxxx xxxx xxxx */
0141     /* LDC2         1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
0142     /* STC2         1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
0143     /* CDP2         1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
0144     /* MCR2         1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
0145     /* MRC2         1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
0146 
0147     /* Other unallocated instructions...                */
0148     DECODE_END
0149 };
0150 
0151 static const union decode_item arm_cccc_0001_0xx0____0xxx_table[] = {
0152     /* Miscellaneous instructions                   */
0153 
0154     /* MRS cpsr     cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
0155     DECODE_SIMULATEX(0x0ff000f0, 0x01000000, PROBES_MRS,
0156                          REGS(0, NOPC, 0, 0, 0)),
0157 
0158     /* BX           cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
0159     DECODE_SIMULATE (0x0ff000f0, 0x01200010, PROBES_BRANCH_REG),
0160 
0161     /* BLX (register)   cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
0162     DECODE_SIMULATEX(0x0ff000f0, 0x01200030, PROBES_BRANCH_REG,
0163                          REGS(0, 0, 0, 0, NOPC)),
0164 
0165     /* CLZ          cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
0166     DECODE_EMULATEX (0x0ff000f0, 0x01600010, PROBES_CLZ,
0167                          REGS(0, NOPC, 0, 0, NOPC)),
0168 
0169     /* QADD         cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx */
0170     /* QSUB         cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx */
0171     /* QDADD        cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx */
0172     /* QDSUB        cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx */
0173     DECODE_EMULATEX (0x0f9000f0, 0x01000050, PROBES_SATURATING_ARITHMETIC,
0174                          REGS(NOPC, NOPC, 0, 0, NOPC)),
0175 
0176     /* BXJ          cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
0177     /* MSR          cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
0178     /* MRS spsr     cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
0179     /* BKPT         1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
0180     /* SMC          cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */
0181     /* And unallocated instructions...              */
0182     DECODE_END
0183 };
0184 
0185 static const union decode_item arm_cccc_0001_0xx0____1xx0_table[] = {
0186     /* Halfword multiply and multiply-accumulate            */
0187 
0188     /* SMLALxy      cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
0189     DECODE_EMULATEX (0x0ff00090, 0x01400080, PROBES_MUL1,
0190                          REGS(NOPC, NOPC, NOPC, 0, NOPC)),
0191 
0192     /* SMULWy       cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
0193     DECODE_OR   (0x0ff000b0, 0x012000a0),
0194     /* SMULxy       cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
0195     DECODE_EMULATEX (0x0ff00090, 0x01600080, PROBES_MUL2,
0196                          REGS(NOPC, 0, NOPC, 0, NOPC)),
0197 
0198     /* SMLAxy       cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx */
0199     DECODE_OR   (0x0ff00090, 0x01000080),
0200     /* SMLAWy       cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx */
0201     DECODE_EMULATEX (0x0ff000b0, 0x01200080, PROBES_MUL2,
0202                          REGS(NOPC, NOPC, NOPC, 0, NOPC)),
0203 
0204     DECODE_END
0205 };
0206 
0207 static const union decode_item arm_cccc_0000_____1001_table[] = {
0208     /* Multiply and multiply-accumulate             */
0209 
0210     /* MUL          cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx */
0211     /* MULS         cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx */
0212     DECODE_EMULATEX (0x0fe000f0, 0x00000090, PROBES_MUL2,
0213                          REGS(NOPC, 0, NOPC, 0, NOPC)),
0214 
0215     /* MLA          cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx */
0216     /* MLAS         cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx */
0217     DECODE_OR   (0x0fe000f0, 0x00200090),
0218     /* MLS          cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx */
0219     DECODE_EMULATEX (0x0ff000f0, 0x00600090, PROBES_MUL2,
0220                          REGS(NOPC, NOPC, NOPC, 0, NOPC)),
0221 
0222     /* UMAAL        cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx */
0223     DECODE_OR   (0x0ff000f0, 0x00400090),
0224     /* UMULL        cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx */
0225     /* UMULLS       cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx */
0226     /* UMLAL        cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx */
0227     /* UMLALS       cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx */
0228     /* SMULL        cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx */
0229     /* SMULLS       cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */
0230     /* SMLAL        cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */
0231     /* SMLALS       cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */
0232     DECODE_EMULATEX (0x0f8000f0, 0x00800090, PROBES_MUL1,
0233                          REGS(NOPC, NOPC, NOPC, 0, NOPC)),
0234 
0235     DECODE_END
0236 };
0237 
0238 static const union decode_item arm_cccc_0001_____1001_table[] = {
0239     /* Synchronization primitives                   */
0240 
0241 #if __LINUX_ARM_ARCH__ < 6
0242     /* Deprecated on ARMv6 and may be UNDEFINED on v7       */
0243     /* SMP/SWPB     cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */
0244     DECODE_EMULATEX (0x0fb000f0, 0x01000090, PROBES_SWP,
0245                          REGS(NOPC, NOPC, 0, 0, NOPC)),
0246 #endif
0247     /* LDREX/STREX{,D,B,H}  cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */
0248     /* And unallocated instructions...              */
0249     DECODE_END
0250 };
0251 
0252 static const union decode_item arm_cccc_000x_____1xx1_table[] = {
0253     /* Extra load/store instructions                */
0254 
0255     /* STRHT        cccc 0000 xx10 xxxx xxxx xxxx 1011 xxxx */
0256     /* ???          cccc 0000 xx10 xxxx xxxx xxxx 11x1 xxxx */
0257     /* LDRHT        cccc 0000 xx11 xxxx xxxx xxxx 1011 xxxx */
0258     /* LDRSBT       cccc 0000 xx11 xxxx xxxx xxxx 1101 xxxx */
0259     /* LDRSHT       cccc 0000 xx11 xxxx xxxx xxxx 1111 xxxx */
0260     DECODE_REJECT   (0x0f200090, 0x00200090),
0261 
0262     /* LDRD/STRD lr,pc,{... cccc 000x x0x0 xxxx 111x xxxx 1101 xxxx */
0263     DECODE_REJECT   (0x0e10e0d0, 0x0000e0d0),
0264 
0265     /* LDRD (register)  cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx */
0266     /* STRD (register)  cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx */
0267     DECODE_EMULATEX (0x0e5000d0, 0x000000d0, PROBES_LDRSTRD,
0268                          REGS(NOPCWB, NOPCX, 0, 0, NOPC)),
0269 
0270     /* LDRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx */
0271     /* STRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx */
0272     DECODE_EMULATEX (0x0e5000d0, 0x004000d0, PROBES_LDRSTRD,
0273                          REGS(NOPCWB, NOPCX, 0, 0, 0)),
0274 
0275     /* STRH (register)  cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx */
0276     DECODE_EMULATEX (0x0e5000f0, 0x000000b0, PROBES_STORE_EXTRA,
0277                          REGS(NOPCWB, NOPC, 0, 0, NOPC)),
0278 
0279     /* LDRH (register)  cccc 000x x0x1 xxxx xxxx xxxx 1011 xxxx */
0280     /* LDRSB (register) cccc 000x x0x1 xxxx xxxx xxxx 1101 xxxx */
0281     /* LDRSH (register) cccc 000x x0x1 xxxx xxxx xxxx 1111 xxxx */
0282     DECODE_EMULATEX (0x0e500090, 0x00100090, PROBES_LOAD_EXTRA,
0283                          REGS(NOPCWB, NOPC, 0, 0, NOPC)),
0284 
0285     /* STRH (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1011 xxxx */
0286     DECODE_EMULATEX (0x0e5000f0, 0x004000b0, PROBES_STORE_EXTRA,
0287                          REGS(NOPCWB, NOPC, 0, 0, 0)),
0288 
0289     /* LDRH (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1011 xxxx */
0290     /* LDRSB (immediate)    cccc 000x x1x1 xxxx xxxx xxxx 1101 xxxx */
0291     /* LDRSH (immediate)    cccc 000x x1x1 xxxx xxxx xxxx 1111 xxxx */
0292     DECODE_EMULATEX (0x0e500090, 0x00500090, PROBES_LOAD_EXTRA,
0293                          REGS(NOPCWB, NOPC, 0, 0, 0)),
0294 
0295     DECODE_END
0296 };
0297 
0298 static const union decode_item arm_cccc_000x_table[] = {
0299     /* Data-processing (register)                   */
0300 
0301     /* <op>S PC, ...    cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */
0302     DECODE_REJECT   (0x0e10f000, 0x0010f000),
0303 
0304     /* MOV IP, SP       1110 0001 1010 0000 1100 0000 0000 1101 */
0305     DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, PROBES_MOV_IP_SP),
0306 
0307     /* TST (register)   cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */
0308     /* TEQ (register)   cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */
0309     /* CMP (register)   cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */
0310     /* CMN (register)   cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */
0311     DECODE_EMULATEX (0x0f900010, 0x01100000, PROBES_DATA_PROCESSING_REG,
0312                          REGS(ANY, 0, 0, 0, ANY)),
0313 
0314     /* MOV (register)   cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */
0315     /* MVN (register)   cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */
0316     DECODE_EMULATEX (0x0fa00010, 0x01a00000, PROBES_DATA_PROCESSING_REG,
0317                          REGS(0, ANY, 0, 0, ANY)),
0318 
0319     /* AND (register)   cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */
0320     /* EOR (register)   cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */
0321     /* SUB (register)   cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */
0322     /* RSB (register)   cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */
0323     /* ADD (register)   cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */
0324     /* ADC (register)   cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */
0325     /* SBC (register)   cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */
0326     /* RSC (register)   cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */
0327     /* ORR (register)   cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */
0328     /* BIC (register)   cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */
0329     DECODE_EMULATEX (0x0e000010, 0x00000000, PROBES_DATA_PROCESSING_REG,
0330                          REGS(ANY, ANY, 0, 0, ANY)),
0331 
0332     /* TST (reg-shift reg)  cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */
0333     /* TEQ (reg-shift reg)  cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */
0334     /* CMP (reg-shift reg)  cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
0335     /* CMN (reg-shift reg)  cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
0336     DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG,
0337                          REGS(NOPC, 0, NOPC, 0, NOPC)),
0338 
0339     /* MOV (reg-shift reg)  cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
0340     /* MVN (reg-shift reg)  cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
0341     DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG,
0342                          REGS(0, NOPC, NOPC, 0, NOPC)),
0343 
0344     /* AND (reg-shift reg)  cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
0345     /* EOR (reg-shift reg)  cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
0346     /* SUB (reg-shift reg)  cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */
0347     /* RSB (reg-shift reg)  cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */
0348     /* ADD (reg-shift reg)  cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */
0349     /* ADC (reg-shift reg)  cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */
0350     /* SBC (reg-shift reg)  cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */
0351     /* RSC (reg-shift reg)  cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */
0352     /* ORR (reg-shift reg)  cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
0353     /* BIC (reg-shift reg)  cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
0354     DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
0355                          REGS(NOPC, NOPC, NOPC, 0, NOPC)),
0356 
0357     DECODE_END
0358 };
0359 
0360 static const union decode_item arm_cccc_001x_table[] = {
0361     /* Data-processing (immediate)                  */
0362 
0363     /* MOVW         cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */
0364     /* MOVT         cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */
0365     DECODE_EMULATEX (0x0fb00000, 0x03000000, PROBES_MOV_HALFWORD,
0366                          REGS(0, NOPC, 0, 0, 0)),
0367 
0368     /* YIELD        cccc 0011 0010 0000 xxxx xxxx 0000 0001 */
0369     DECODE_OR   (0x0fff00ff, 0x03200001),
0370     /* SEV          cccc 0011 0010 0000 xxxx xxxx 0000 0100 */
0371     DECODE_EMULATE  (0x0fff00ff, 0x03200004, PROBES_SEV),
0372     /* NOP          cccc 0011 0010 0000 xxxx xxxx 0000 0000 */
0373     /* WFE          cccc 0011 0010 0000 xxxx xxxx 0000 0010 */
0374     /* WFI          cccc 0011 0010 0000 xxxx xxxx 0000 0011 */
0375     DECODE_SIMULATE (0x0fff00fc, 0x03200000, PROBES_WFE),
0376     /* DBG          cccc 0011 0010 0000 xxxx xxxx ffff xxxx */
0377     /* unallocated hints    cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */
0378     /* MSR (immediate)  cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx */
0379     DECODE_REJECT   (0x0fb00000, 0x03200000),
0380 
0381     /* <op>S PC, ...    cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */
0382     DECODE_REJECT   (0x0e10f000, 0x0210f000),
0383 
0384     /* TST (immediate)  cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx */
0385     /* TEQ (immediate)  cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx */
0386     /* CMP (immediate)  cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx */
0387     /* CMN (immediate)  cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx */
0388     DECODE_EMULATEX (0x0f900000, 0x03100000, PROBES_DATA_PROCESSING_IMM,
0389                          REGS(ANY, 0, 0, 0, 0)),
0390 
0391     /* MOV (immediate)  cccc 0011 101x xxxx xxxx xxxx xxxx xxxx */
0392     /* MVN (immediate)  cccc 0011 111x xxxx xxxx xxxx xxxx xxxx */
0393     DECODE_EMULATEX (0x0fa00000, 0x03a00000, PROBES_DATA_PROCESSING_IMM,
0394                          REGS(0, ANY, 0, 0, 0)),
0395 
0396     /* AND (immediate)  cccc 0010 000x xxxx xxxx xxxx xxxx xxxx */
0397     /* EOR (immediate)  cccc 0010 001x xxxx xxxx xxxx xxxx xxxx */
0398     /* SUB (immediate)  cccc 0010 010x xxxx xxxx xxxx xxxx xxxx */
0399     /* RSB (immediate)  cccc 0010 011x xxxx xxxx xxxx xxxx xxxx */
0400     /* ADD (immediate)  cccc 0010 100x xxxx xxxx xxxx xxxx xxxx */
0401     /* ADC (immediate)  cccc 0010 101x xxxx xxxx xxxx xxxx xxxx */
0402     /* SBC (immediate)  cccc 0010 110x xxxx xxxx xxxx xxxx xxxx */
0403     /* RSC (immediate)  cccc 0010 111x xxxx xxxx xxxx xxxx xxxx */
0404     /* ORR (immediate)  cccc 0011 100x xxxx xxxx xxxx xxxx xxxx */
0405     /* BIC (immediate)  cccc 0011 110x xxxx xxxx xxxx xxxx xxxx */
0406     DECODE_EMULATEX (0x0e000000, 0x02000000, PROBES_DATA_PROCESSING_IMM,
0407                          REGS(ANY, ANY, 0, 0, 0)),
0408 
0409     DECODE_END
0410 };
0411 
0412 static const union decode_item arm_cccc_0110_____xxx1_table[] = {
0413     /* Media instructions                       */
0414 
0415     /* SEL          cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx */
0416     DECODE_EMULATEX (0x0ff000f0, 0x068000b0, PROBES_SATURATE,
0417                          REGS(NOPC, NOPC, 0, 0, NOPC)),
0418 
0419     /* SSAT         cccc 0110 101x xxxx xxxx xxxx xx01 xxxx */
0420     /* USAT         cccc 0110 111x xxxx xxxx xxxx xx01 xxxx */
0421     DECODE_OR(0x0fa00030, 0x06a00010),
0422     /* SSAT16       cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx */
0423     /* USAT16       cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx */
0424     DECODE_EMULATEX (0x0fb000f0, 0x06a00030, PROBES_SATURATE,
0425                          REGS(0, NOPC, 0, 0, NOPC)),
0426 
0427     /* REV          cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
0428     /* REV16        cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
0429     /* RBIT         cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */
0430     /* REVSH        cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
0431     DECODE_EMULATEX (0x0fb00070, 0x06b00030, PROBES_REV,
0432                          REGS(0, NOPC, 0, 0, NOPC)),
0433 
0434     /* ???          cccc 0110 0x00 xxxx xxxx xxxx xxx1 xxxx */
0435     DECODE_REJECT   (0x0fb00010, 0x06000010),
0436     /* ???          cccc 0110 0xxx xxxx xxxx xxxx 1011 xxxx */
0437     DECODE_REJECT   (0x0f8000f0, 0x060000b0),
0438     /* ???          cccc 0110 0xxx xxxx xxxx xxxx 1101 xxxx */
0439     DECODE_REJECT   (0x0f8000f0, 0x060000d0),
0440     /* SADD16       cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx */
0441     /* SADDSUBX     cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx */
0442     /* SSUBADDX     cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx */
0443     /* SSUB16       cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx */
0444     /* SADD8        cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx */
0445     /* SSUB8        cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx */
0446     /* QADD16       cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx */
0447     /* QADDSUBX     cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx */
0448     /* QSUBADDX     cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx */
0449     /* QSUB16       cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx */
0450     /* QADD8        cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx */
0451     /* QSUB8        cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx */
0452     /* SHADD16      cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx */
0453     /* SHADDSUBX        cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx */
0454     /* SHSUBADDX        cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx */
0455     /* SHSUB16      cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx */
0456     /* SHADD8       cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx */
0457     /* SHSUB8       cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx */
0458     /* UADD16       cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx */
0459     /* UADDSUBX     cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx */
0460     /* USUBADDX     cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx */
0461     /* USUB16       cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx */
0462     /* UADD8        cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx */
0463     /* USUB8        cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx */
0464     /* UQADD16      cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx */
0465     /* UQADDSUBX        cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx */
0466     /* UQSUBADDX        cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx */
0467     /* UQSUB16      cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx */
0468     /* UQADD8       cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx */
0469     /* UQSUB8       cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx */
0470     /* UHADD16      cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx */
0471     /* UHADDSUBX        cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx */
0472     /* UHSUBADDX        cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx */
0473     /* UHSUB16      cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx */
0474     /* UHADD8       cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx */
0475     /* UHSUB8       cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx */
0476     DECODE_EMULATEX (0x0f800010, 0x06000010, PROBES_MMI,
0477                          REGS(NOPC, NOPC, 0, 0, NOPC)),
0478 
0479     /* PKHBT        cccc 0110 1000 xxxx xxxx xxxx x001 xxxx */
0480     /* PKHTB        cccc 0110 1000 xxxx xxxx xxxx x101 xxxx */
0481     DECODE_EMULATEX (0x0ff00030, 0x06800010, PROBES_PACK,
0482                          REGS(NOPC, NOPC, 0, 0, NOPC)),
0483 
0484     /* ???          cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx */
0485     /* ???          cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx */
0486     DECODE_REJECT   (0x0fb000f0, 0x06900070),
0487 
0488     /* SXTB16       cccc 0110 1000 1111 xxxx xxxx 0111 xxxx */
0489     /* SXTB         cccc 0110 1010 1111 xxxx xxxx 0111 xxxx */
0490     /* SXTH         cccc 0110 1011 1111 xxxx xxxx 0111 xxxx */
0491     /* UXTB16       cccc 0110 1100 1111 xxxx xxxx 0111 xxxx */
0492     /* UXTB         cccc 0110 1110 1111 xxxx xxxx 0111 xxxx */
0493     /* UXTH         cccc 0110 1111 1111 xxxx xxxx 0111 xxxx */
0494     DECODE_EMULATEX (0x0f8f00f0, 0x068f0070, PROBES_EXTEND,
0495                          REGS(0, NOPC, 0, 0, NOPC)),
0496 
0497     /* SXTAB16      cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx */
0498     /* SXTAB        cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx */
0499     /* SXTAH        cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx */
0500     /* UXTAB16      cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx */
0501     /* UXTAB        cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx */
0502     /* UXTAH        cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx */
0503     DECODE_EMULATEX (0x0f8000f0, 0x06800070, PROBES_EXTEND_ADD,
0504                          REGS(NOPCX, NOPC, 0, 0, NOPC)),
0505 
0506     DECODE_END
0507 };
0508 
0509 static const union decode_item arm_cccc_0111_____xxx1_table[] = {
0510     /* Media instructions                       */
0511 
0512     /* UNDEFINED        cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
0513     DECODE_REJECT   (0x0ff000f0, 0x07f000f0),
0514 
0515     /* SMLALD       cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
0516     /* SMLSLD       cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
0517     DECODE_EMULATEX (0x0ff00090, 0x07400010, PROBES_MUL_ADD_LONG,
0518                          REGS(NOPC, NOPC, NOPC, 0, NOPC)),
0519 
0520     /* SMUAD        cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */
0521     /* SMUSD        cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */
0522     DECODE_OR   (0x0ff0f090, 0x0700f010),
0523     /* SMMUL        cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx */
0524     DECODE_OR   (0x0ff0f0d0, 0x0750f010),
0525     /* USAD8        cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
0526     DECODE_EMULATEX (0x0ff0f0f0, 0x0780f010, PROBES_MUL_ADD,
0527                          REGS(NOPC, 0, NOPC, 0, NOPC)),
0528 
0529     /* SMLAD        cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx */
0530     /* SMLSD        cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx */
0531     DECODE_OR   (0x0ff00090, 0x07000010),
0532     /* SMMLA        cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx */
0533     DECODE_OR   (0x0ff000d0, 0x07500010),
0534     /* USADA8       cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
0535     DECODE_EMULATEX (0x0ff000f0, 0x07800010, PROBES_MUL_ADD,
0536                          REGS(NOPC, NOPCX, NOPC, 0, NOPC)),
0537 
0538     /* SMMLS        cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx */
0539     DECODE_EMULATEX (0x0ff000d0, 0x075000d0, PROBES_MUL_ADD,
0540                          REGS(NOPC, NOPC, NOPC, 0, NOPC)),
0541 
0542     /* SBFX         cccc 0111 101x xxxx xxxx xxxx x101 xxxx */
0543     /* UBFX         cccc 0111 111x xxxx xxxx xxxx x101 xxxx */
0544     DECODE_EMULATEX (0x0fa00070, 0x07a00050, PROBES_BITFIELD,
0545                          REGS(0, NOPC, 0, 0, NOPC)),
0546 
0547     /* BFC          cccc 0111 110x xxxx xxxx xxxx x001 1111 */
0548     DECODE_EMULATEX (0x0fe0007f, 0x07c0001f, PROBES_BITFIELD,
0549                          REGS(0, NOPC, 0, 0, 0)),
0550 
0551     /* BFI          cccc 0111 110x xxxx xxxx xxxx x001 xxxx */
0552     DECODE_EMULATEX (0x0fe00070, 0x07c00010, PROBES_BITFIELD,
0553                          REGS(0, NOPC, 0, 0, NOPCX)),
0554 
0555     DECODE_END
0556 };
0557 
0558 static const union decode_item arm_cccc_01xx_table[] = {
0559     /* Load/store word and unsigned byte                */
0560 
0561     /* LDRB/STRB pc,[...]   cccc 01xx x0xx xxxx xxxx xxxx xxxx xxxx */
0562     DECODE_REJECT   (0x0c40f000, 0x0440f000),
0563 
0564     /* STRT         cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
0565     /* LDRT         cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
0566     /* STRBT        cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
0567     /* LDRBT        cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
0568     DECODE_REJECT   (0x0d200000, 0x04200000),
0569 
0570     /* STR (immediate)  cccc 010x x0x0 xxxx xxxx xxxx xxxx xxxx */
0571     /* STRB (immediate) cccc 010x x1x0 xxxx xxxx xxxx xxxx xxxx */
0572     DECODE_EMULATEX (0x0e100000, 0x04000000, PROBES_STORE,
0573                          REGS(NOPCWB, ANY, 0, 0, 0)),
0574 
0575     /* LDR (immediate)  cccc 010x x0x1 xxxx xxxx xxxx xxxx xxxx */
0576     /* LDRB (immediate) cccc 010x x1x1 xxxx xxxx xxxx xxxx xxxx */
0577     DECODE_EMULATEX (0x0e100000, 0x04100000, PROBES_LOAD,
0578                          REGS(NOPCWB, ANY, 0, 0, 0)),
0579 
0580     /* STR (register)   cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx */
0581     /* STRB (register)  cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx */
0582     DECODE_EMULATEX (0x0e100000, 0x06000000, PROBES_STORE,
0583                          REGS(NOPCWB, ANY, 0, 0, NOPC)),
0584 
0585     /* LDR (register)   cccc 011x x0x1 xxxx xxxx xxxx xxxx xxxx */
0586     /* LDRB (register)  cccc 011x x1x1 xxxx xxxx xxxx xxxx xxxx */
0587     DECODE_EMULATEX (0x0e100000, 0x06100000, PROBES_LOAD,
0588                          REGS(NOPCWB, ANY, 0, 0, NOPC)),
0589 
0590     DECODE_END
0591 };
0592 
0593 static const union decode_item arm_cccc_100x_table[] = {
0594     /* Block data transfer instructions             */
0595 
0596     /* LDM          cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
0597     /* STM          cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
0598     DECODE_CUSTOM   (0x0e400000, 0x08000000, PROBES_LDMSTM),
0599 
0600     /* STM (user registers) cccc 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
0601     /* LDM (user registers) cccc 100x x1x1 xxxx 0xxx xxxx xxxx xxxx */
0602     /* LDM (exception ret)  cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
0603     DECODE_END
0604 };
0605 
0606 const union decode_item probes_decode_arm_table[] = {
0607     /*
0608      * Unconditional instructions
0609      *          1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx
0610      */
0611     DECODE_TABLE    (0xf0000000, 0xf0000000, arm_1111_table),
0612 
0613     /*
0614      * Miscellaneous instructions
0615      *          cccc 0001 0xx0 xxxx xxxx xxxx 0xxx xxxx
0616      */
0617     DECODE_TABLE    (0x0f900080, 0x01000000, arm_cccc_0001_0xx0____0xxx_table),
0618 
0619     /*
0620      * Halfword multiply and multiply-accumulate
0621      *          cccc 0001 0xx0 xxxx xxxx xxxx 1xx0 xxxx
0622      */
0623     DECODE_TABLE    (0x0f900090, 0x01000080, arm_cccc_0001_0xx0____1xx0_table),
0624 
0625     /*
0626      * Multiply and multiply-accumulate
0627      *          cccc 0000 xxxx xxxx xxxx xxxx 1001 xxxx
0628      */
0629     DECODE_TABLE    (0x0f0000f0, 0x00000090, arm_cccc_0000_____1001_table),
0630 
0631     /*
0632      * Synchronization primitives
0633      *          cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx
0634      */
0635     DECODE_TABLE    (0x0f0000f0, 0x01000090, arm_cccc_0001_____1001_table),
0636 
0637     /*
0638      * Extra load/store instructions
0639      *          cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx
0640      */
0641     DECODE_TABLE    (0x0e000090, 0x00000090, arm_cccc_000x_____1xx1_table),
0642 
0643     /*
0644      * Data-processing (register)
0645      *          cccc 000x xxxx xxxx xxxx xxxx xxx0 xxxx
0646      * Data-processing (register-shifted register)
0647      *          cccc 000x xxxx xxxx xxxx xxxx 0xx1 xxxx
0648      */
0649     DECODE_TABLE    (0x0e000000, 0x00000000, arm_cccc_000x_table),
0650 
0651     /*
0652      * Data-processing (immediate)
0653      *          cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
0654      */
0655     DECODE_TABLE    (0x0e000000, 0x02000000, arm_cccc_001x_table),
0656 
0657     /*
0658      * Media instructions
0659      *          cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx
0660      */
0661     DECODE_TABLE    (0x0f000010, 0x06000010, arm_cccc_0110_____xxx1_table),
0662     DECODE_TABLE    (0x0f000010, 0x07000010, arm_cccc_0111_____xxx1_table),
0663 
0664     /*
0665      * Load/store word and unsigned byte
0666      *          cccc 01xx xxxx xxxx xxxx xxxx xxxx xxxx
0667      */
0668     DECODE_TABLE    (0x0c000000, 0x04000000, arm_cccc_01xx_table),
0669 
0670     /*
0671      * Block data transfer instructions
0672      *          cccc 100x xxxx xxxx xxxx xxxx xxxx xxxx
0673      */
0674     DECODE_TABLE    (0x0e000000, 0x08000000, arm_cccc_100x_table),
0675 
0676     /* B            cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
0677     /* BL           cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
0678     DECODE_SIMULATE (0x0e000000, 0x0a000000, PROBES_BRANCH),
0679 
0680     /*
0681      * Supervisor Call, and coprocessor instructions
0682      */
0683 
0684     /* MCRR         cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx */
0685     /* MRRC         cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx */
0686     /* LDC          cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
0687     /* STC          cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
0688     /* CDP          cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
0689     /* MCR          cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
0690     /* MRC          cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
0691     /* SVC          cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
0692     DECODE_REJECT   (0x0c000000, 0x0c000000),
0693 
0694     DECODE_END
0695 };
0696 #ifdef CONFIG_ARM_KPROBES_TEST_MODULE
0697 EXPORT_SYMBOL_GPL(probes_decode_arm_table);
0698 #endif
0699 
0700 static void __kprobes arm_singlestep(probes_opcode_t insn,
0701         struct arch_probes_insn *asi, struct pt_regs *regs)
0702 {
0703     regs->ARM_pc += 4;
0704     asi->insn_handler(insn, asi, regs);
0705 }
0706 
0707 /* Return:
0708  *   INSN_REJECTED     If instruction is one not allowed to kprobe,
0709  *   INSN_GOOD         If instruction is supported and uses instruction slot,
0710  *   INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
0711  *
0712  * For instructions we don't want to kprobe (INSN_REJECTED return result):
0713  *   These are generally ones that modify the processor state making
0714  *   them "hard" to simulate such as switches processor modes or
0715  *   make accesses in alternate modes.  Any of these could be simulated
0716  *   if the work was put into it, but low return considering they
0717  *   should also be very rare.
0718  */
0719 enum probes_insn __kprobes
0720 arm_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
0721                bool emulate, const union decode_action *actions,
0722                const struct decode_checker *checkers[])
0723 {
0724     asi->insn_singlestep = arm_singlestep;
0725     asi->insn_check_cc = probes_condition_checks[insn>>28];
0726     return probes_decode_insn(insn, asi, probes_decode_arm_table, false,
0727                   emulate, actions, checkers);
0728 }
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