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0001 /*
0002  * arch/arm/plat-orion/gpio.c
0003  *
0004  * Marvell Orion SoC GPIO handling.
0005  *
0006  * This file is licensed under the terms of the GNU General Public
0007  * License version 2.  This program is licensed "as is" without any
0008  * warranty of any kind, whether express or implied.
0009  */
0010 
0011 #define DEBUG
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/init.h>
0015 #include <linux/irq.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/module.h>
0018 #include <linux/spinlock.h>
0019 #include <linux/bitops.h>
0020 #include <linux/io.h>
0021 #include <linux/gpio.h>
0022 #include <linux/leds.h>
0023 #include <linux/of.h>
0024 #include <linux/of_irq.h>
0025 #include <linux/of_address.h>
0026 #include <plat/orion-gpio.h>
0027 
0028 /*
0029  * GPIO unit register offsets.
0030  */
0031 #define GPIO_OUT_OFF        0x0000
0032 #define GPIO_IO_CONF_OFF    0x0004
0033 #define GPIO_BLINK_EN_OFF   0x0008
0034 #define GPIO_IN_POL_OFF     0x000c
0035 #define GPIO_DATA_IN_OFF    0x0010
0036 #define GPIO_EDGE_CAUSE_OFF 0x0014
0037 #define GPIO_EDGE_MASK_OFF  0x0018
0038 #define GPIO_LEVEL_MASK_OFF 0x001c
0039 
0040 struct orion_gpio_chip {
0041     struct gpio_chip    chip;
0042     spinlock_t      lock;
0043     void __iomem        *base;
0044     unsigned long       valid_input;
0045     unsigned long       valid_output;
0046     int         mask_offset;
0047     int         secondary_irq_base;
0048     struct irq_domain       *domain;
0049 };
0050 
0051 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
0052 {
0053     return ochip->base + GPIO_OUT_OFF;
0054 }
0055 
0056 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
0057 {
0058     return ochip->base + GPIO_IO_CONF_OFF;
0059 }
0060 
0061 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
0062 {
0063     return ochip->base + GPIO_BLINK_EN_OFF;
0064 }
0065 
0066 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
0067 {
0068     return ochip->base + GPIO_IN_POL_OFF;
0069 }
0070 
0071 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
0072 {
0073     return ochip->base + GPIO_DATA_IN_OFF;
0074 }
0075 
0076 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
0077 {
0078     return ochip->base + GPIO_EDGE_CAUSE_OFF;
0079 }
0080 
0081 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
0082 {
0083     return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
0084 }
0085 
0086 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
0087 {
0088     return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
0089 }
0090 
0091 
0092 static struct orion_gpio_chip orion_gpio_chips[2];
0093 static int orion_gpio_chip_count;
0094 
0095 static inline void
0096 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
0097 {
0098     u32 u;
0099 
0100     u = readl(GPIO_IO_CONF(ochip));
0101     if (input)
0102         u |= 1 << pin;
0103     else
0104         u &= ~(1 << pin);
0105     writel(u, GPIO_IO_CONF(ochip));
0106 }
0107 
0108 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
0109 {
0110     u32 u;
0111 
0112     u = readl(GPIO_OUT(ochip));
0113     if (high)
0114         u |= 1 << pin;
0115     else
0116         u &= ~(1 << pin);
0117     writel(u, GPIO_OUT(ochip));
0118 }
0119 
0120 static inline void
0121 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
0122 {
0123     u32 u;
0124 
0125     u = readl(GPIO_BLINK_EN(ochip));
0126     if (blink)
0127         u |= 1 << pin;
0128     else
0129         u &= ~(1 << pin);
0130     writel(u, GPIO_BLINK_EN(ochip));
0131 }
0132 
0133 static inline int
0134 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
0135 {
0136     if (pin >= ochip->chip.ngpio)
0137         goto err_out;
0138 
0139     if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
0140         goto err_out;
0141 
0142     if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
0143         goto err_out;
0144 
0145     return 1;
0146 
0147 err_out:
0148     pr_debug("%s: invalid GPIO %d\n", __func__, pin);
0149     return false;
0150 }
0151 
0152 /*
0153  * GPIO primitives.
0154  */
0155 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
0156 {
0157     struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
0158 
0159     if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
0160         orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
0161         return 0;
0162 
0163     return -EINVAL;
0164 }
0165 
0166 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
0167 {
0168     struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
0169     unsigned long flags;
0170 
0171     if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
0172         return -EINVAL;
0173 
0174     spin_lock_irqsave(&ochip->lock, flags);
0175     __set_direction(ochip, pin, 1);
0176     spin_unlock_irqrestore(&ochip->lock, flags);
0177 
0178     return 0;
0179 }
0180 
0181 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
0182 {
0183     struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
0184     int val;
0185 
0186     if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
0187         val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
0188     } else {
0189         val = readl(GPIO_OUT(ochip));
0190     }
0191 
0192     return (val >> pin) & 1;
0193 }
0194 
0195 static int
0196 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
0197 {
0198     struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
0199     unsigned long flags;
0200 
0201     if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
0202         return -EINVAL;
0203 
0204     spin_lock_irqsave(&ochip->lock, flags);
0205     __set_blinking(ochip, pin, 0);
0206     __set_level(ochip, pin, value);
0207     __set_direction(ochip, pin, 0);
0208     spin_unlock_irqrestore(&ochip->lock, flags);
0209 
0210     return 0;
0211 }
0212 
0213 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
0214 {
0215     struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
0216     unsigned long flags;
0217 
0218     spin_lock_irqsave(&ochip->lock, flags);
0219     __set_level(ochip, pin, value);
0220     spin_unlock_irqrestore(&ochip->lock, flags);
0221 }
0222 
0223 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
0224 {
0225     struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
0226 
0227     return irq_create_mapping(ochip->domain,
0228                   ochip->secondary_irq_base + pin);
0229 }
0230 
0231 /*
0232  * Orion-specific GPIO API extensions.
0233  */
0234 static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
0235 {
0236     int i;
0237 
0238     for (i = 0; i < orion_gpio_chip_count; i++) {
0239         struct orion_gpio_chip *ochip = orion_gpio_chips + i;
0240         struct gpio_chip *chip = &ochip->chip;
0241 
0242         if (pin >= chip->base && pin < chip->base + chip->ngpio)
0243             return ochip;
0244     }
0245 
0246     return NULL;
0247 }
0248 
0249 void __init orion_gpio_set_unused(unsigned pin)
0250 {
0251     struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
0252 
0253     if (ochip == NULL)
0254         return;
0255 
0256     pin -= ochip->chip.base;
0257 
0258     /* Configure as output, drive low. */
0259     __set_level(ochip, pin, 0);
0260     __set_direction(ochip, pin, 0);
0261 }
0262 
0263 void __init orion_gpio_set_valid(unsigned pin, int mode)
0264 {
0265     struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
0266 
0267     if (ochip == NULL)
0268         return;
0269 
0270     pin -= ochip->chip.base;
0271 
0272     if (mode == 1)
0273         mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
0274 
0275     if (mode & GPIO_INPUT_OK)
0276         __set_bit(pin, &ochip->valid_input);
0277     else
0278         __clear_bit(pin, &ochip->valid_input);
0279 
0280     if (mode & GPIO_OUTPUT_OK)
0281         __set_bit(pin, &ochip->valid_output);
0282     else
0283         __clear_bit(pin, &ochip->valid_output);
0284 }
0285 
0286 void orion_gpio_set_blink(unsigned pin, int blink)
0287 {
0288     struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
0289     unsigned long flags;
0290 
0291     if (ochip == NULL)
0292         return;
0293 
0294     spin_lock_irqsave(&ochip->lock, flags);
0295     __set_level(ochip, pin & 31, 0);
0296     __set_blinking(ochip, pin & 31, blink);
0297     spin_unlock_irqrestore(&ochip->lock, flags);
0298 }
0299 EXPORT_SYMBOL(orion_gpio_set_blink);
0300 
0301 #define ORION_BLINK_HALF_PERIOD 100 /* ms */
0302 
0303 int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
0304     unsigned long *delay_on, unsigned long *delay_off)
0305 {
0306     unsigned gpio = desc_to_gpio(desc);
0307 
0308     if (delay_on && delay_off && !*delay_on && !*delay_off)
0309         *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
0310 
0311     switch (state) {
0312     case GPIO_LED_NO_BLINK_LOW:
0313     case GPIO_LED_NO_BLINK_HIGH:
0314         orion_gpio_set_blink(gpio, 0);
0315         gpio_set_value(gpio, state);
0316         break;
0317     case GPIO_LED_BLINK:
0318         orion_gpio_set_blink(gpio, 1);
0319     }
0320     return 0;
0321 }
0322 EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
0323 
0324 
0325 /*****************************************************************************
0326  * Orion GPIO IRQ
0327  *
0328  * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
0329  * value of the line or the opposite value.
0330  *
0331  * Level IRQ handlers: DATA_IN is used directly as cause register.
0332  *                     Interrupt are masked by LEVEL_MASK registers.
0333  * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
0334  *                     Interrupt are masked by EDGE_MASK registers.
0335  * Both-edge handlers: Similar to regular Edge handlers, but also swaps
0336  *                     the polarity to catch the next line transaction.
0337  *                     This is a race condition that might not perfectly
0338  *                     work on some use cases.
0339  *
0340  * Every eight GPIO lines are grouped (OR'ed) before going up to main
0341  * cause register.
0342  *
0343  *                    EDGE  cause    mask
0344  *        data-in   /--------| |-----| |----\
0345  *     -----| |-----                         ---- to main cause reg
0346  *           X      \----------------| |----/
0347  *        polarity    LEVEL          mask
0348  *
0349  ****************************************************************************/
0350 
0351 static int gpio_irq_set_type(struct irq_data *d, u32 type)
0352 {
0353     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0354     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0355     struct orion_gpio_chip *ochip = gc->private;
0356     int pin;
0357     u32 u;
0358 
0359     pin = d->hwirq - ochip->secondary_irq_base;
0360 
0361     u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
0362     if (!u) {
0363         return -EINVAL;
0364     }
0365 
0366     type &= IRQ_TYPE_SENSE_MASK;
0367     if (type == IRQ_TYPE_NONE)
0368         return -EINVAL;
0369 
0370     /* Check if we need to change chip and handler */
0371     if (!(ct->type & type))
0372         if (irq_setup_alt_chip(d, type))
0373             return -EINVAL;
0374 
0375     /*
0376      * Configure interrupt polarity.
0377      */
0378     if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
0379         u = readl(GPIO_IN_POL(ochip));
0380         u &= ~(1 << pin);
0381         writel(u, GPIO_IN_POL(ochip));
0382     } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
0383         u = readl(GPIO_IN_POL(ochip));
0384         u |= 1 << pin;
0385         writel(u, GPIO_IN_POL(ochip));
0386     } else if (type == IRQ_TYPE_EDGE_BOTH) {
0387         u32 v;
0388 
0389         v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
0390 
0391         /*
0392          * set initial polarity based on current input level
0393          */
0394         u = readl(GPIO_IN_POL(ochip));
0395         if (v & (1 << pin))
0396             u |= 1 << pin;      /* falling */
0397         else
0398             u &= ~(1 << pin);   /* rising */
0399         writel(u, GPIO_IN_POL(ochip));
0400     }
0401     return 0;
0402 }
0403 
0404 static void gpio_irq_handler(struct irq_desc *desc)
0405 {
0406     struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
0407     u32 cause, type;
0408     int i;
0409 
0410     if (ochip == NULL)
0411         return;
0412 
0413     cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
0414     cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
0415 
0416     for (i = 0; i < ochip->chip.ngpio; i++) {
0417         int irq;
0418 
0419         irq = ochip->secondary_irq_base + i;
0420 
0421         if (!(cause & (1 << i)))
0422             continue;
0423 
0424         type = irq_get_trigger_type(irq);
0425         if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
0426             /* Swap polarity (race with GPIO line) */
0427             u32 polarity;
0428 
0429             polarity = readl(GPIO_IN_POL(ochip));
0430             polarity ^= 1 << i;
0431             writel(polarity, GPIO_IN_POL(ochip));
0432         }
0433         generic_handle_irq(irq);
0434     }
0435 }
0436 
0437 #ifdef CONFIG_DEBUG_FS
0438 #include <linux/seq_file.h>
0439 
0440 static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0441 {
0442 
0443     struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
0444     u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
0445     const char *label;
0446     int i;
0447 
0448     out = readl_relaxed(GPIO_OUT(ochip));
0449     io_conf = readl_relaxed(GPIO_IO_CONF(ochip));
0450     blink   = readl_relaxed(GPIO_BLINK_EN(ochip));
0451     in_pol  = readl_relaxed(GPIO_IN_POL(ochip));
0452     data_in = readl_relaxed(GPIO_DATA_IN(ochip));
0453     cause   = readl_relaxed(GPIO_EDGE_CAUSE(ochip));
0454     edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
0455     lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
0456 
0457     for_each_requested_gpio(chip, i, label) {
0458         u32 msk;
0459         bool is_out;
0460 
0461         msk = 1 << i;
0462         is_out = !(io_conf & msk);
0463 
0464         seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
0465 
0466         if (is_out) {
0467             seq_printf(s, " out %s %s\n",
0468                    out & msk ? "hi" : "lo",
0469                    blink & msk ? "(blink )" : "");
0470             continue;
0471         }
0472 
0473         seq_printf(s, " in  %s (act %s) - IRQ",
0474                (data_in ^ in_pol) & msk  ? "hi" : "lo",
0475                in_pol & msk ? "lo" : "hi");
0476         if (!((edg_msk | lvl_msk) & msk)) {
0477             seq_puts(s, " disabled\n");
0478             continue;
0479         }
0480         if (edg_msk & msk)
0481             seq_puts(s, " edge ");
0482         if (lvl_msk & msk)
0483             seq_puts(s, " level");
0484         seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
0485     }
0486 }
0487 #else
0488 #define orion_gpio_dbg_show NULL
0489 #endif
0490 
0491 static void orion_gpio_unmask_irq(struct irq_data *d)
0492 {
0493     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0494     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0495     u32 reg_val;
0496     u32 mask = d->mask;
0497 
0498     irq_gc_lock(gc);
0499     reg_val = irq_reg_readl(gc, ct->regs.mask);
0500     reg_val |= mask;
0501     irq_reg_writel(gc, reg_val, ct->regs.mask);
0502     irq_gc_unlock(gc);
0503 }
0504 
0505 static void orion_gpio_mask_irq(struct irq_data *d)
0506 {
0507     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0508     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0509     u32 mask = d->mask;
0510     u32 reg_val;
0511 
0512     irq_gc_lock(gc);
0513     reg_val = irq_reg_readl(gc, ct->regs.mask);
0514     reg_val &= ~mask;
0515     irq_reg_writel(gc, reg_val, ct->regs.mask);
0516     irq_gc_unlock(gc);
0517 }
0518 
0519 void __init orion_gpio_init(int gpio_base, int ngpio,
0520                 void __iomem *base, int mask_offset,
0521                 int secondary_irq_base,
0522                 int irqs[4])
0523 {
0524     struct orion_gpio_chip *ochip;
0525     struct irq_chip_generic *gc;
0526     struct irq_chip_type *ct;
0527     char gc_label[16];
0528     int i;
0529 
0530     if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
0531         return;
0532 
0533     snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
0534         orion_gpio_chip_count);
0535 
0536     ochip = orion_gpio_chips + orion_gpio_chip_count;
0537     ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
0538     ochip->chip.request = orion_gpio_request;
0539     ochip->chip.direction_input = orion_gpio_direction_input;
0540     ochip->chip.get = orion_gpio_get;
0541     ochip->chip.direction_output = orion_gpio_direction_output;
0542     ochip->chip.set = orion_gpio_set;
0543     ochip->chip.to_irq = orion_gpio_to_irq;
0544     ochip->chip.base = gpio_base;
0545     ochip->chip.ngpio = ngpio;
0546     ochip->chip.can_sleep = 0;
0547     ochip->chip.dbg_show = orion_gpio_dbg_show;
0548 
0549     spin_lock_init(&ochip->lock);
0550     ochip->base = (void __iomem *)base;
0551     ochip->valid_input = 0;
0552     ochip->valid_output = 0;
0553     ochip->mask_offset = mask_offset;
0554     ochip->secondary_irq_base = secondary_irq_base;
0555 
0556     gpiochip_add_data(&ochip->chip, ochip);
0557 
0558     /*
0559      * Mask and clear GPIO interrupts.
0560      */
0561     writel(0, GPIO_EDGE_CAUSE(ochip));
0562     writel(0, GPIO_EDGE_MASK(ochip));
0563     writel(0, GPIO_LEVEL_MASK(ochip));
0564 
0565     /* Setup the interrupt handlers. Each chip can have up to 4
0566      * interrupt handlers, with each handler dealing with 8 GPIO
0567      * pins. */
0568 
0569     for (i = 0; i < 4; i++) {
0570         if (irqs[i]) {
0571             irq_set_chained_handler_and_data(irqs[i],
0572                              gpio_irq_handler,
0573                              ochip);
0574         }
0575     }
0576 
0577     gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
0578                     secondary_irq_base,
0579                     ochip->base, handle_level_irq);
0580     gc->private = ochip;
0581     ct = gc->chip_types;
0582     ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
0583     ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
0584     ct->chip.irq_mask = orion_gpio_mask_irq;
0585     ct->chip.irq_unmask = orion_gpio_unmask_irq;
0586     ct->chip.irq_set_type = gpio_irq_set_type;
0587     ct->chip.name = ochip->chip.label;
0588 
0589     ct++;
0590     ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
0591     ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
0592     ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
0593     ct->chip.irq_ack = irq_gc_ack_clr_bit;
0594     ct->chip.irq_mask = orion_gpio_mask_irq;
0595     ct->chip.irq_unmask = orion_gpio_unmask_irq;
0596     ct->chip.irq_set_type = gpio_irq_set_type;
0597     ct->handler = handle_edge_irq;
0598     ct->chip.name = ochip->chip.label;
0599 
0600     irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
0601                    IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
0602 
0603     /* Setup irq domain on top of the generic chip. */
0604     ochip->domain = irq_domain_add_legacy(NULL,
0605                           ochip->chip.ngpio,
0606                           ochip->secondary_irq_base,
0607                           ochip->secondary_irq_base,
0608                           &irq_domain_simple_ops,
0609                           ochip);
0610     if (!ochip->domain)
0611         panic("%s: couldn't allocate irq domain (DT).\n",
0612               ochip->chip.label);
0613 
0614     orion_gpio_chip_count++;
0615 }
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