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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */ 0002 /* 0003 NetWinder Floating Point Emulator 0004 (c) Rebel.com, 1998-1999 0005 0006 Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 0007 0008 */ 0009 0010 #ifndef __FPSR_H__ 0011 #define __FPSR_H__ 0012 0013 /* 0014 The FPSR is a 32 bit register consisting of 4 parts, each exactly 0015 one byte. 0016 0017 SYSTEM ID 0018 EXCEPTION TRAP ENABLE BYTE 0019 SYSTEM CONTROL BYTE 0020 CUMULATIVE EXCEPTION FLAGS BYTE 0021 0022 The FPCR is a 32 bit register consisting of bit flags. 0023 */ 0024 0025 /* SYSTEM ID 0026 ------------ 0027 Note: the system id byte is read only */ 0028 0029 typedef unsigned int FPSR; /* type for floating point status register */ 0030 typedef unsigned int FPCR; /* type for floating point control register */ 0031 0032 #define MASK_SYSID 0xff000000 0033 #define BIT_HARDWARE 0x80000000 0034 #define FP_EMULATOR 0x01000000 /* System ID for emulator */ 0035 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ 0036 0037 /* EXCEPTION TRAP ENABLE BYTE 0038 ----------------------------- */ 0039 0040 #define MASK_TRAP_ENABLE 0x00ff0000 0041 #define MASK_TRAP_ENABLE_STRICT 0x001f0000 0042 #define BIT_IXE 0x00100000 /* inexact exception enable */ 0043 #define BIT_UFE 0x00080000 /* underflow exception enable */ 0044 #define BIT_OFE 0x00040000 /* overflow exception enable */ 0045 #define BIT_DZE 0x00020000 /* divide by zero exception enable */ 0046 #define BIT_IOE 0x00010000 /* invalid operation exception enable */ 0047 0048 /* SYSTEM CONTROL BYTE 0049 ---------------------- */ 0050 0051 #define MASK_SYSTEM_CONTROL 0x0000ff00 0052 #define MASK_TRAP_STRICT 0x00001f00 0053 0054 #define BIT_AC 0x00001000 /* use alternative C-flag definition 0055 for compares */ 0056 #define BIT_EP 0x00000800 /* use expanded packed decimal format */ 0057 #define BIT_SO 0x00000400 /* select synchronous operation of FPA */ 0058 #define BIT_NE 0x00000200 /* NaN exception bit */ 0059 #define BIT_ND 0x00000100 /* no denormalized numbers bit */ 0060 0061 /* CUMULATIVE EXCEPTION FLAGS BYTE 0062 ---------------------------------- */ 0063 0064 #define MASK_EXCEPTION_FLAGS 0x000000ff 0065 #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f 0066 0067 #define BIT_IXC 0x00000010 /* inexact exception flag */ 0068 #define BIT_UFC 0x00000008 /* underflow exception flag */ 0069 #define BIT_OFC 0x00000004 /* overfloat exception flag */ 0070 #define BIT_DZC 0x00000002 /* divide by zero exception flag */ 0071 #define BIT_IOC 0x00000001 /* invalid operation exception flag */ 0072 0073 /* Floating Point Control Register 0074 ----------------------------------*/ 0075 0076 #define BIT_RU 0x80000000 /* rounded up bit */ 0077 #define BIT_IE 0x10000000 /* inexact bit */ 0078 #define BIT_MO 0x08000000 /* mantissa overflow bit */ 0079 #define BIT_EO 0x04000000 /* exponent overflow bit */ 0080 #define BIT_SB 0x00000800 /* store bounce */ 0081 #define BIT_AB 0x00000400 /* arithmetic bounce */ 0082 #define BIT_RE 0x00000200 /* rounding exception */ 0083 #define BIT_DA 0x00000100 /* disable FPA */ 0084 0085 #define MASK_OP 0x00f08010 /* AU operation code */ 0086 #define MASK_PR 0x00080080 /* AU precision */ 0087 #define MASK_S1 0x00070000 /* AU source register 1 */ 0088 #define MASK_S2 0x00000007 /* AU source register 2 */ 0089 #define MASK_DS 0x00007000 /* AU destination register */ 0090 #define MASK_RM 0x00000060 /* AU rounding mode */ 0091 #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */ 0092 #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */ 0093 #define MASK_WFC MASK_RESET 0094 #define MASK_RFC ~MASK_RESET 0095 0096 #endif
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