arm/mm/tlb-v7.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/arch/arm/mm/tlb-v7.S
0004  *
0005  *  Copyright (C) 1997-2002 Russell King
0006  *  Modified for ARMv7 by Catalin Marinas
0007  *
0008  *  ARM architecture version 6 TLB handling functions.
0009  *  These assume a split I/D TLB.
0010  */
0011 #include <linux/init.h>
0012 #include <linux/linkage.h>
0013 #include <asm/assembler.h>
0014 #include <asm/asm-offsets.h>
0015 #include <asm/page.h>
0016 #include <asm/tlbflush.h>
0017 #include "proc-macros.S"
0018
0019 /*
0020  *  v7wbi_flush_user_tlb_range(start, end, vma)
0021  *
0022  *  Invalidate a range of TLB entries in the specified address space.
0023  *
0024  *  - start - start address (may not be aligned)
0025  *  - end   - end address (exclusive, may not be aligned)
0026  *  - vma   - vm_area_struct describing address range
0027  *
0028  *  It is assumed that:
0029  *  - the "Invalidate single entry" instruction will invalidate
0030  *    both the I and the D TLBs on Harvard-style TLBs
0031  */
0032 ENTRY(v7wbi_flush_user_tlb_range)
0033     vma_vm_mm r3, r2            @ get vma->vm_mm
0034     mmid    r3, r3              @ get vm_mm->context.id
0035     dsb ish
0036     mov r0, r0, lsr #PAGE_SHIFT     @ align address
0037     mov r1, r1, lsr #PAGE_SHIFT
0038     asid    r3, r3              @ mask ASID
0039 #ifdef CONFIG_ARM_ERRATA_720789
0040     ALT_SMP(W(mov)  r3, #0  )
0041     ALT_UP(W(nop)       )
0042 #endif
0043     orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
0044     mov r1, r1, lsl #PAGE_SHIFT
0045 1:
0046 #ifdef CONFIG_ARM_ERRATA_720789
0047     ALT_SMP(mcr p15, 0, r0, c8, c3, 3)  @ TLB invalidate U MVA all ASID (shareable)
0048 #else
0049     ALT_SMP(mcr p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
0050 #endif
0051     ALT_UP(mcr  p15, 0, r0, c8, c7, 1)  @ TLB invalidate U MVA
0052
0053     add r0, r0, #PAGE_SZ
0054     cmp r0, r1
0055     blo 1b
0056     dsb ish
0057     ret lr
0058 ENDPROC(v7wbi_flush_user_tlb_range)
0059
0060 /*
0061  *  v7wbi_flush_kern_tlb_range(start,end)
0062  *
0063  *  Invalidate a range of kernel TLB entries
0064  *
0065  *  - start - start address (may not be aligned)
0066  *  - end   - end address (exclusive, may not be aligned)
0067  */
0068 ENTRY(v7wbi_flush_kern_tlb_range)
0069     dsb ish
0070     mov r0, r0, lsr #PAGE_SHIFT     @ align address
0071     mov r1, r1, lsr #PAGE_SHIFT
0072     mov r0, r0, lsl #PAGE_SHIFT
0073     mov r1, r1, lsl #PAGE_SHIFT
0074 1:
0075 #ifdef CONFIG_ARM_ERRATA_720789
0076     ALT_SMP(mcr p15, 0, r0, c8, c3, 3)  @ TLB invalidate U MVA all ASID (shareable)
0077 #else
0078     ALT_SMP(mcr p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
0079 #endif
0080     ALT_UP(mcr  p15, 0, r0, c8, c7, 1)  @ TLB invalidate U MVA
0081     add r0, r0, #PAGE_SZ
0082     cmp r0, r1
0083     blo 1b
0084     dsb ish
0085     isb
0086     ret lr
0087 ENDPROC(v7wbi_flush_kern_tlb_range)
0088
0089     __INIT
0090
0091     /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
0092     define_tlb_functions v7wbi, v7wbi_tlb_flags_up, flags_smp=v7wbi_tlb_flags_smp