arm/mm/tlb-v6.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/arch/arm/mm/tlb-v6.S
0004  *
0005  *  Copyright (C) 1997-2002 Russell King
0006  *
0007  *  ARM architecture version 6 TLB handling functions.
0008  *  These assume a split I/D TLB.
0009  */
0010 #include <linux/init.h>
0011 #include <linux/linkage.h>
0012 #include <asm/asm-offsets.h>
0013 #include <asm/assembler.h>
0014 #include <asm/page.h>
0015 #include <asm/tlbflush.h>
0016 #include "proc-macros.S"
0017
0018 #define HARVARD_TLB
0019
0020 /*
0021  *  v6wbi_flush_user_tlb_range(start, end, vma)
0022  *
0023  *  Invalidate a range of TLB entries in the specified address space.
0024  *
0025  *  - start - start address (may not be aligned)
0026  *  - end   - end address (exclusive, may not be aligned)
0027  *  - vma   - vm_area_struct describing address range
0028  *
0029  *  It is assumed that:
0030  *  - the "Invalidate single entry" instruction will invalidate
0031  *    both the I and the D TLBs on Harvard-style TLBs
0032  */
0033 ENTRY(v6wbi_flush_user_tlb_range)
0034     vma_vm_mm r3, r2            @ get vma->vm_mm
0035     mov ip, #0
0036     mmid    r3, r3              @ get vm_mm->context.id
0037     mcr p15, 0, ip, c7, c10, 4      @ drain write buffer
0038     mov r0, r0, lsr #PAGE_SHIFT     @ align address
0039     mov r1, r1, lsr #PAGE_SHIFT
0040     asid    r3, r3              @ mask ASID
0041     orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
0042     mov r1, r1, lsl #PAGE_SHIFT
0043     vma_vm_flags r2, r2         @ get vma->vm_flags
0044 1:
0045 #ifdef HARVARD_TLB
0046     mcr p15, 0, r0, c8, c6, 1       @ TLB invalidate D MVA (was 1)
0047     tst r2, #VM_EXEC            @ Executable area ?
0048     mcrne   p15, 0, r0, c8, c5, 1       @ TLB invalidate I MVA (was 1)
0049 #else
0050     mcr p15, 0, r0, c8, c7, 1       @ TLB invalidate MVA (was 1)
0051 #endif
0052     add r0, r0, #PAGE_SZ
0053     cmp r0, r1
0054     blo 1b
0055     mcr p15, 0, ip, c7, c10, 4      @ data synchronization barrier
0056     ret lr
0057
0058 /*
0059  *  v6wbi_flush_kern_tlb_range(start,end)
0060  *
0061  *  Invalidate a range of kernel TLB entries
0062  *
0063  *  - start - start address (may not be aligned)
0064  *  - end   - end address (exclusive, may not be aligned)
0065  */
0066 ENTRY(v6wbi_flush_kern_tlb_range)
0067     mov r2, #0
0068     mcr p15, 0, r2, c7, c10, 4      @ drain write buffer
0069     mov r0, r0, lsr #PAGE_SHIFT     @ align address
0070     mov r1, r1, lsr #PAGE_SHIFT
0071     mov r0, r0, lsl #PAGE_SHIFT
0072     mov r1, r1, lsl #PAGE_SHIFT
0073 1:
0074 #ifdef HARVARD_TLB
0075     mcr p15, 0, r0, c8, c6, 1       @ TLB invalidate D MVA
0076     mcr p15, 0, r0, c8, c5, 1       @ TLB invalidate I MVA
0077 #else
0078     mcr p15, 0, r0, c8, c7, 1       @ TLB invalidate MVA
0079 #endif
0080     add r0, r0, #PAGE_SZ
0081     cmp r0, r1
0082     blo 1b
0083     mcr p15, 0, r2, c7, c10, 4      @ data synchronization barrier
0084     mcr p15, 0, r2, c7, c5, 4       @ prefetch flush (isb)
0085     ret lr
0086
0087     __INIT
0088
0089     /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
0090     define_tlb_functions v6wbi, v6wbi_tlb_flags