arm/mm/tlb-v4wb.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/arch/arm/mm/tlbv4wb.S
0004  *
0005  *  Copyright (C) 1997-2002 Russell King
0006  *
0007  *  ARM architecture version 4 TLB handling functions.
0008  *  These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
0009  *
0010  *  Processors: SA110 SA1100 SA1110
0011  */
0012 #include <linux/linkage.h>
0013 #include <linux/init.h>
0014 #include <asm/assembler.h>
0015 #include <asm/asm-offsets.h>
0016 #include <asm/tlbflush.h>
0017 #include "proc-macros.S"
0018
0019     .align  5
0020 /*
0021  *  v4wb_flush_user_tlb_range(start, end, mm)
0022  *
0023  *  Invalidate a range of TLB entries in the specified address space.
0024  *
0025  *  - start - range start address
0026  *  - end   - range end address
0027  *  - mm    - mm_struct describing address space
0028  */
0029     .align  5
0030 ENTRY(v4wb_flush_user_tlb_range)
0031     vma_vm_mm ip, r2
0032     act_mm  r3              @ get current->active_mm
0033     eors    r3, ip, r3              @ == mm ?
0034     retne   lr              @ no, we dont do anything
0035     vma_vm_flags r2, r2
0036     mcr p15, 0, r3, c7, c10, 4      @ drain WB
0037     tst r2, #VM_EXEC
0038     mcrne   p15, 0, r3, c8, c5, 0       @ invalidate I TLB
0039     bic r0, r0, #0x0ff
0040     bic r0, r0, #0xf00
0041 1:  mcr p15, 0, r0, c8, c6, 1       @ invalidate D TLB entry
0042     add r0, r0, #PAGE_SZ
0043     cmp r0, r1
0044     blo 1b
0045     ret lr
0046
0047 /*
0048  *  v4_flush_kern_tlb_range(start, end)
0049  *
0050  *  Invalidate a range of TLB entries in the specified kernel
0051  *  address range.
0052  *
0053  *  - start - virtual address (may not be aligned)
0054  *  - end   - virtual address (may not be aligned)
0055  */
0056 ENTRY(v4wb_flush_kern_tlb_range)
0057     mov r3, #0
0058     mcr p15, 0, r3, c7, c10, 4      @ drain WB
0059     bic r0, r0, #0x0ff
0060     bic r0, r0, #0xf00
0061     mcr p15, 0, r3, c8, c5, 0       @ invalidate I TLB
0062 1:  mcr p15, 0, r0, c8, c6, 1       @ invalidate D TLB entry
0063     add r0, r0, #PAGE_SZ
0064     cmp r0, r1
0065     blo 1b
0066     ret lr
0067
0068     __INITDATA
0069
0070     /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
0071     define_tlb_functions v4wb, v4wb_tlb_flags