arm/mm/proc-v7-2level.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * arch/arm/mm/proc-v7-2level.S
0004  *
0005  * Copyright (C) 2001 Deep Blue Solutions Ltd.
0006  */
0007
0008 #define TTB_S       (1 << 1)
0009 #define TTB_RGN_NC  (0 << 3)
0010 #define TTB_RGN_OC_WBWA (1 << 3)
0011 #define TTB_RGN_OC_WT   (2 << 3)
0012 #define TTB_RGN_OC_WB   (3 << 3)
0013 #define TTB_NOS     (1 << 5)
0014 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
0015 #define TTB_IRGN_WBWA   ((0 << 0) | (1 << 6))
0016 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
0017 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
0018
0019 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
0020 #define TTB_FLAGS_UP    TTB_IRGN_WB|TTB_RGN_OC_WB
0021 #define PMD_FLAGS_UP    PMD_SECT_WB
0022
0023 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
0024 #define TTB_FLAGS_SMP   TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
0025 #define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
0026
0027 /*
0028  *  cpu_v7_switch_mm(pgd_phys, tsk)
0029  *
0030  *  Set the translation table base pointer to be pgd_phys
0031  *
0032  *  - pgd_phys - physical address of new TTB
0033  *
0034  *  It is assumed that:
0035  *  - we are not using split page tables
0036  *
0037  *  Note that we always need to flush BTAC/BTB if IBE is set
0038  *  even on Cortex-A8 revisions not affected by 430973.
0039  *  If IBE is not set, the flush BTAC/BTB won't do anything.
0040  */
0041 ENTRY(cpu_v7_switch_mm)
0042 #ifdef CONFIG_MMU
0043     mmid    r1, r1              @ get mm->context.id
0044     ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
0045     ALT_UP(orr  r0, r0, #TTB_FLAGS_UP)
0046 #ifdef CONFIG_PID_IN_CONTEXTIDR
0047     mrc p15, 0, r2, c13, c0, 1      @ read current context ID
0048     lsr r2, r2, #8          @ extract the PID
0049     bfi r1, r2, #8, #24         @ insert into new context ID
0050 #endif
0051 #ifdef CONFIG_ARM_ERRATA_754322
0052     dsb
0053 #endif
0054     mcr p15, 0, r1, c13, c0, 1      @ set context ID
0055     isb
0056     mcr p15, 0, r0, c2, c0, 0       @ set TTB 0
0057     isb
0058 #endif
0059     bx  lr
0060 ENDPROC(cpu_v7_switch_mm)
0061
0062 /*
0063  *  cpu_v7_set_pte_ext(ptep, pte)
0064  *
0065  *  Set a level 2 translation table entry.
0066  *
0067  *  - ptep  - pointer to level 2 translation table entry
0068  *        (hardware version is stored at +2048 bytes)
0069  *  - pte   - PTE value to store
0070  *  - ext   - value for extended PTE bits
0071  */
0072 ENTRY(cpu_v7_set_pte_ext)
0073 #ifdef CONFIG_MMU
0074     str r1, [r0]            @ linux version
0075
0076     bic r3, r1, #0x000003f0
0077     bic r3, r3, #PTE_TYPE_MASK
0078     orr r3, r3, r2
0079     orr r3, r3, #PTE_EXT_AP0 | 2
0080
0081     tst r1, #1 << 4
0082     orrne   r3, r3, #PTE_EXT_TEX(1)
0083
0084     eor r1, r1, #L_PTE_DIRTY
0085     tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
0086     orrne   r3, r3, #PTE_EXT_APX
0087
0088     tst r1, #L_PTE_USER
0089     orrne   r3, r3, #PTE_EXT_AP1
0090
0091     tst r1, #L_PTE_XN
0092     orrne   r3, r3, #PTE_EXT_XN
0093
0094     tst r1, #L_PTE_YOUNG
0095     tstne   r1, #L_PTE_VALID
0096     eorne   r1, r1, #L_PTE_NONE
0097     tstne   r1, #L_PTE_NONE
0098     moveq   r3, #0
0099
0100  ARM(   str r3, [r0, #2048]! )
0101  THUMB( add r0, r0, #2048 )
0102  THUMB( str r3, [r0] )
0103     ALT_SMP(W(nop))
0104     ALT_UP (mcr p15, 0, r0, c7, c10, 1)     @ flush_pte
0105 #endif
0106     bx  lr
0107 ENDPROC(cpu_v7_set_pte_ext)
0108
0109     /*
0110      * Memory region attributes with SCTLR.TRE=1
0111      *
0112      *   n = TEX[0],C,B
0113      *   TR = PRRR[2n+1:2n]     - memory type
0114      *   IR = NMRR[2n+1:2n]     - inner cacheable property
0115      *   OR = NMRR[2n+17:2n+16] - outer cacheable property
0116      *
0117      *          n   TR  IR  OR
0118      *   UNCACHED       000 00
0119      *   BUFFERABLE     001 10  00  00
0120      *   WRITETHROUGH   010 10  10  10
0121      *   WRITEBACK      011 10  11  11
0122      *   reserved       110
0123      *   WRITEALLOC     111 10  01  01
0124      *   DEV_SHARED     100 01
0125      *   DEV_NONSHARED  100 01
0126      *   DEV_WC     001 10
0127      *   DEV_CACHED     011 10
0128      *
0129      * Other attributes:
0130      *
0131      *   DS0 = PRRR[16] = 0     - device shareable property
0132      *   DS1 = PRRR[17] = 1     - device shareable property
0133      *   NS0 = PRRR[18] = 0     - normal shareable property
0134      *   NS1 = PRRR[19] = 1     - normal shareable property
0135      *   NOS = PRRR[24+n] = 1   - not outer shareable
0136      */
0137 .equ    PRRR,   0xff0a81a8
0138 .equ    NMRR,   0x40e040e0
0139
0140     /*
0141      * Macro for setting up the TTBRx and TTBCR registers.
0142      * - \ttb0 and \ttb1 updated with the corresponding flags.
0143      */
0144     .macro  v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
0145     mcr p15, 0, \zero, c2, c0, 2    @ TTB control register
0146     ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
0147     ALT_UP(orr  \ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
0148     ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
0149     ALT_UP(orr  \ttbr1, \ttbr1, #TTB_FLAGS_UP)
0150     mcr p15, 0, \ttbr1, c2, c0, 1   @ load TTB1
0151     .endm
0152
0153     /*   AT
0154      *  TFR   EV X F   I D LR    S
0155      * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
0156      * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
0157      *   01    0 110       0011 1100 .111 1101 < we want
0158      */
0159     .align  2
0160     .type   v7_crval, #object
0161 v7_crval:
0162     crval   clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c