arm/mm/proc-v6.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/arch/arm/mm/proc-v6.S
0004  *
0005  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
0006  *  Modified by Catalin Marinas for noMMU support
0007  *
0008  *  This is the "shell" of the ARMv6 processor support.
0009  */
0010 #include <linux/init.h>
0011 #include <linux/linkage.h>
0012 #include <linux/pgtable.h>
0013 #include <asm/assembler.h>
0014 #include <asm/asm-offsets.h>
0015 #include <asm/hwcap.h>
0016 #include <asm/pgtable-hwdef.h>
0017
0018 #include "proc-macros.S"
0019
0020 #define D_CACHE_LINE_SIZE   32
0021
0022 #define TTB_C       (1 << 0)
0023 #define TTB_S       (1 << 1)
0024 #define TTB_IMP     (1 << 2)
0025 #define TTB_RGN_NC  (0 << 3)
0026 #define TTB_RGN_WBWA    (1 << 3)
0027 #define TTB_RGN_WT  (2 << 3)
0028 #define TTB_RGN_WB  (3 << 3)
0029
0030 #define TTB_FLAGS_UP    TTB_RGN_WBWA
0031 #define PMD_FLAGS_UP    PMD_SECT_WB
0032 #define TTB_FLAGS_SMP   TTB_RGN_WBWA|TTB_S
0033 #define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
0034
0035 ENTRY(cpu_v6_proc_init)
0036     ret lr
0037
0038 ENTRY(cpu_v6_proc_fin)
0039     mrc p15, 0, r0, c1, c0, 0       @ ctrl register
0040     bic r0, r0, #0x1000         @ ...i............
0041     bic r0, r0, #0x0006         @ .............ca.
0042     mcr p15, 0, r0, c1, c0, 0       @ disable caches
0043     ret lr
0044
0045 /*
0046  *  cpu_v6_reset(loc)
0047  *
0048  *  Perform a soft reset of the system.  Put the CPU into the
0049  *  same state as it would be if it had been reset, and branch
0050  *  to what would be the reset vector.
0051  *
0052  *  - loc   - location to jump to for soft reset
0053  */
0054     .align  5
0055     .pushsection    .idmap.text, "ax"
0056 ENTRY(cpu_v6_reset)
0057     mrc p15, 0, r1, c1, c0, 0       @ ctrl register
0058     bic r1, r1, #0x1            @ ...............m
0059     mcr p15, 0, r1, c1, c0, 0       @ disable MMU
0060     mov r1, #0
0061     mcr p15, 0, r1, c7, c5, 4       @ ISB
0062     ret r0
0063 ENDPROC(cpu_v6_reset)
0064     .popsection
0065
0066 /*
0067  *  cpu_v6_do_idle()
0068  *
0069  *  Idle the processor (eg, wait for interrupt).
0070  *
0071  *  IRQs are already disabled.
0072  */
0073 ENTRY(cpu_v6_do_idle)
0074     mov r1, #0
0075     mcr p15, 0, r1, c7, c10, 4      @ DWB - WFI may enter a low-power mode
0076     mcr p15, 0, r1, c7, c0, 4       @ wait for interrupt
0077     ret lr
0078
0079 ENTRY(cpu_v6_dcache_clean_area)
0080 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0081     add r0, r0, #D_CACHE_LINE_SIZE
0082     subs    r1, r1, #D_CACHE_LINE_SIZE
0083     bhi 1b
0084     ret lr
0085
0086 /*
0087  *  cpu_v6_switch_mm(pgd_phys, tsk)
0088  *
0089  *  Set the translation table base pointer to be pgd_phys
0090  *
0091  *  - pgd_phys - physical address of new TTB
0092  *
0093  *  It is assumed that:
0094  *  - we are not using split page tables
0095  */
0096 ENTRY(cpu_v6_switch_mm)
0097 #ifdef CONFIG_MMU
0098     mov r2, #0
0099     mmid    r1, r1              @ get mm->context.id
0100     ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
0101     ALT_UP(orr  r0, r0, #TTB_FLAGS_UP)
0102     mcr p15, 0, r2, c7, c5, 6       @ flush BTAC/BTB
0103     mcr p15, 0, r2, c7, c10, 4      @ drain write buffer
0104     mcr p15, 0, r0, c2, c0, 0       @ set TTB 0
0105 #ifdef CONFIG_PID_IN_CONTEXTIDR
0106     mrc p15, 0, r2, c13, c0, 1      @ read current context ID
0107     bic r2, r2, #0xff           @ extract the PID
0108     and r1, r1, #0xff
0109     orr r1, r1, r2          @ insert into new context ID
0110 #endif
0111     mcr p15, 0, r1, c13, c0, 1      @ set context ID
0112 #endif
0113     ret lr
0114
0115 /*
0116  *  cpu_v6_set_pte_ext(ptep, pte, ext)
0117  *
0118  *  Set a level 2 translation table entry.
0119  *
0120  *  - ptep  - pointer to level 2 translation table entry
0121  *        (hardware version is stored at -1024 bytes)
0122  *  - pte   - PTE value to store
0123  *  - ext   - value for extended PTE bits
0124  */
0125     armv6_mt_table cpu_v6
0126
0127 ENTRY(cpu_v6_set_pte_ext)
0128 #ifdef CONFIG_MMU
0129     armv6_set_pte_ext cpu_v6
0130 #endif
0131     ret lr
0132
0133 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
0134 .globl  cpu_v6_suspend_size
0135 .equ    cpu_v6_suspend_size, 4 * 6
0136 #ifdef CONFIG_ARM_CPU_SUSPEND
0137 ENTRY(cpu_v6_do_suspend)
0138     stmfd   sp!, {r4 - r9, lr}
0139     mrc p15, 0, r4, c13, c0, 0  @ FCSE/PID
0140 #ifdef CONFIG_MMU
0141     mrc p15, 0, r5, c3, c0, 0   @ Domain ID
0142     mrc p15, 0, r6, c2, c0, 1   @ Translation table base 1
0143 #endif
0144     mrc p15, 0, r7, c1, c0, 1   @ auxiliary control register
0145     mrc p15, 0, r8, c1, c0, 2   @ co-processor access control
0146     mrc p15, 0, r9, c1, c0, 0   @ control register
0147     stmia   r0, {r4 - r9}
0148     ldmfd   sp!, {r4- r9, pc}
0149 ENDPROC(cpu_v6_do_suspend)
0150
0151 ENTRY(cpu_v6_do_resume)
0152     mov ip, #0
0153     mcr p15, 0, ip, c7, c14, 0  @ clean+invalidate D cache
0154     mcr p15, 0, ip, c7, c5, 0   @ invalidate I cache
0155     mcr p15, 0, ip, c7, c15, 0  @ clean+invalidate cache
0156     mcr p15, 0, ip, c7, c10, 4  @ drain write buffer
0157     mcr p15, 0, ip, c13, c0, 1  @ set reserved context ID
0158     ldmia   r0, {r4 - r9}
0159     mcr p15, 0, r4, c13, c0, 0  @ FCSE/PID
0160 #ifdef CONFIG_MMU
0161     mcr p15, 0, r5, c3, c0, 0   @ Domain ID
0162     ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
0163     ALT_UP(orr  r1, r1, #TTB_FLAGS_UP)
0164     mcr p15, 0, r1, c2, c0, 0   @ Translation table base 0
0165     mcr p15, 0, r6, c2, c0, 1   @ Translation table base 1
0166     mcr p15, 0, ip, c2, c0, 2   @ TTB control register
0167 #endif
0168     mcr p15, 0, r7, c1, c0, 1   @ auxiliary control register
0169     mcr p15, 0, r8, c1, c0, 2   @ co-processor access control
0170     mcr p15, 0, ip, c7, c5, 4   @ ISB
0171     mov r0, r9          @ control register
0172     b   cpu_resume_mmu
0173 ENDPROC(cpu_v6_do_resume)
0174 #endif
0175
0176     string  cpu_v6_name, "ARMv6-compatible processor"
0177
0178     .align
0179
0180 /*
0181  *  __v6_setup
0182  *
0183  *  Initialise TLB, Caches, and MMU state ready to switch the MMU
0184  *  on.  Return in r0 the new CP15 C1 control register setting.
0185  *
0186  *  We automatically detect if we have a Harvard cache, and use the
0187  *  Harvard cache control instructions insead of the unified cache
0188  *  control instructions.
0189  *
0190  *  This should be able to cover all ARMv6 cores.
0191  *
0192  *  It is assumed that:
0193  *  - cache type register is implemented
0194  */
0195 __v6_setup:
0196 #ifdef CONFIG_SMP
0197     ALT_SMP(mrc p15, 0, r0, c1, c0, 1)  @ Enable SMP/nAMP mode
0198     ALT_UP(nop)
0199     orr r0, r0, #0x20
0200     ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
0201     ALT_UP(nop)
0202 #endif
0203
0204     mov r0, #0
0205     mcr p15, 0, r0, c7, c14, 0      @ clean+invalidate D cache
0206     mcr p15, 0, r0, c7, c5, 0       @ invalidate I cache
0207     mcr p15, 0, r0, c7, c15, 0      @ clean+invalidate cache
0208 #ifdef CONFIG_MMU
0209     mcr p15, 0, r0, c8, c7, 0       @ invalidate I + D TLBs
0210     mcr p15, 0, r0, c2, c0, 2       @ TTB control register
0211     ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
0212     ALT_UP(orr  r4, r4, #TTB_FLAGS_UP)
0213     ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
0214     ALT_UP(orr  r8, r8, #TTB_FLAGS_UP)
0215     mcr p15, 0, r8, c2, c0, 1       @ load TTB1
0216 #endif /* CONFIG_MMU */
0217     mcr p15, 0, r0, c7, c10, 4      @ drain write buffer and
0218                         @ complete invalidations
0219     adr r5, v6_crval
0220     ldmia   r5, {r5, r6}
0221  ARM_BE8(orr    r6, r6, #1 << 25)       @ big-endian page tables
0222     mrc p15, 0, r0, c1, c0, 0       @ read control register
0223     bic r0, r0, r5          @ clear bits them
0224     orr r0, r0, r6          @ set them
0225 #ifdef CONFIG_ARM_ERRATA_364296
0226     /*
0227      * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
0228      * corruption with hit-under-miss enabled). The conditional code below
0229      * (setting the undocumented bit 31 in the auxiliary control register
0230      * and the FI bit in the control register) disables hit-under-miss
0231      * without putting the processor into full low interrupt latency mode.
0232      */
0233     ldr r6, =0x4107b362         @ id for ARM1136 r0p2
0234     mrc p15, 0, r5, c0, c0, 0       @ get processor id
0235     teq r5, r6              @ check for the faulty core
0236     mrceq   p15, 0, r5, c1, c0, 1       @ load aux control reg
0237     orreq   r5, r5, #(1 << 31)      @ set the undocumented bit 31
0238     mcreq   p15, 0, r5, c1, c0, 1       @ write aux control reg
0239     orreq   r0, r0, #(1 << 21)      @ low interrupt latency configuration
0240 #endif
0241     ret lr              @ return to head.S:__ret
0242
0243     /*
0244      *         V X F   I D LR
0245      * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
0246      * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
0247      *         0 110       0011 1.00 .111 1101 < we want
0248      */
0249     .type   v6_crval, #object
0250 v6_crval:
0251     crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
0252
0253     __INITDATA
0254
0255     @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
0256     define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
0257
0258     .section ".rodata"
0259
0260     string  cpu_arch_name, "armv6"
0261     string  cpu_elf_name, "v6"
0262     .align
0263
0264     .section ".proc.info.init", "a"
0265
0266     /*
0267      * Match any ARMv6 processor core.
0268      */
0269     .type   __v6_proc_info, #object
0270 __v6_proc_info:
0271     .long   0x0007b000
0272     .long   0x0007f000
0273     ALT_SMP(.long \
0274         PMD_TYPE_SECT | \
0275         PMD_SECT_AP_WRITE | \
0276         PMD_SECT_AP_READ | \
0277         PMD_FLAGS_SMP)
0278     ALT_UP(.long \
0279         PMD_TYPE_SECT | \
0280         PMD_SECT_AP_WRITE | \
0281         PMD_SECT_AP_READ | \
0282         PMD_FLAGS_UP)
0283     .long   PMD_TYPE_SECT | \
0284         PMD_SECT_XN | \
0285         PMD_SECT_AP_WRITE | \
0286         PMD_SECT_AP_READ
0287     initfn  __v6_setup, __v6_proc_info
0288     .long   cpu_arch_name
0289     .long   cpu_elf_name
0290     /* See also feat_v6_fixup() for HWCAP_TLS */
0291     .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
0292     .long   cpu_v6_name
0293     .long   v6_processor_functions
0294     .long   v6wbi_tlb_fns
0295     .long   v6_user_fns
0296     .long   v6_cache_fns
0297     .size   __v6_proc_info, . - __v6_proc_info