arm/mm/proc-fa526.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
0004  *
0005  *  Written by : Luke Lee
0006  *  Copyright (C) 2005 Faraday Corp.
0007  *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
0008  *
0009  * These are the low level assembler for performing cache and TLB
0010  * functions on the fa526.
0011  */
0012 #include <linux/linkage.h>
0013 #include <linux/init.h>
0014 #include <linux/pgtable.h>
0015 #include <asm/assembler.h>
0016 #include <asm/hwcap.h>
0017 #include <asm/pgtable-hwdef.h>
0018 #include <asm/page.h>
0019 #include <asm/ptrace.h>
0020
0021 #include "proc-macros.S"
0022
0023 #define CACHE_DLINESIZE 16
0024
0025     .text
0026 /*
0027  * cpu_fa526_proc_init()
0028  */
0029 ENTRY(cpu_fa526_proc_init)
0030     ret lr
0031
0032 /*
0033  * cpu_fa526_proc_fin()
0034  */
0035 ENTRY(cpu_fa526_proc_fin)
0036     mrc p15, 0, r0, c1, c0, 0       @ ctrl register
0037     bic r0, r0, #0x1000         @ ...i............
0038     bic r0, r0, #0x000e         @ ............wca.
0039     mcr p15, 0, r0, c1, c0, 0       @ disable caches
0040     nop
0041     nop
0042     ret lr
0043
0044 /*
0045  * cpu_fa526_reset(loc)
0046  *
0047  * Perform a soft reset of the system.  Put the CPU into the
0048  * same state as it would be if it had been reset, and branch
0049  * to what would be the reset vector.
0050  *
0051  * loc: location to jump to for soft reset
0052  */
0053     .align  4
0054     .pushsection    .idmap.text, "ax"
0055 ENTRY(cpu_fa526_reset)
0056 /* TODO: Use CP8 if possible... */
0057     mov ip, #0
0058     mcr p15, 0, ip, c7, c7, 0       @ invalidate I,D caches
0059     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0060 #ifdef CONFIG_MMU
0061     mcr p15, 0, ip, c8, c7, 0       @ invalidate I & D TLBs
0062 #endif
0063     mrc p15, 0, ip, c1, c0, 0       @ ctrl register
0064     bic ip, ip, #0x000f         @ ............wcam
0065     bic ip, ip, #0x1100         @ ...i...s........
0066     bic ip, ip, #0x0800         @ BTB off
0067     mcr p15, 0, ip, c1, c0, 0       @ ctrl register
0068     nop
0069     nop
0070     ret r0
0071 ENDPROC(cpu_fa526_reset)
0072     .popsection
0073
0074 /*
0075  * cpu_fa526_do_idle()
0076  */
0077     .align  4
0078 ENTRY(cpu_fa526_do_idle)
0079     ret lr
0080
0081
0082 ENTRY(cpu_fa526_dcache_clean_area)
0083 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0084     add r0, r0, #CACHE_DLINESIZE
0085     subs    r1, r1, #CACHE_DLINESIZE
0086     bhi 1b
0087     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0088     ret lr
0089
0090 /* =============================== PageTable ============================== */
0091
0092 /*
0093  * cpu_fa526_switch_mm(pgd)
0094  *
0095  * Set the translation base pointer to be as described by pgd.
0096  *
0097  * pgd: new page tables
0098  */
0099     .align  4
0100 ENTRY(cpu_fa526_switch_mm)
0101 #ifdef CONFIG_MMU
0102     mov ip, #0
0103 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
0104     mcr p15, 0, ip, c7, c6, 0       @ invalidate D cache
0105 #else
0106     mcr p15, 0, ip, c7, c14, 0      @ clean and invalidate whole D cache
0107 #endif
0108     mcr p15, 0, ip, c7, c5, 0       @ invalidate I cache
0109     mcr p15, 0, ip, c7, c5, 6       @ invalidate BTB since mm changed
0110     mcr p15, 0, ip, c7, c10, 4      @ data write barrier
0111     mcr p15, 0, ip, c7, c5, 4       @ prefetch flush
0112     mcr p15, 0, r0, c2, c0, 0       @ load page table pointer
0113     mcr p15, 0, ip, c8, c7, 0       @ invalidate UTLB
0114 #endif
0115     ret lr
0116
0117 /*
0118  * cpu_fa526_set_pte_ext(ptep, pte, ext)
0119  *
0120  * Set a PTE and flush it out
0121  */
0122     .align  4
0123 ENTRY(cpu_fa526_set_pte_ext)
0124 #ifdef CONFIG_MMU
0125     armv3_set_pte_ext
0126     mov r0, r0
0127     mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0128     mov r0, #0
0129     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0130 #endif
0131     ret lr
0132
0133     .type   __fa526_setup, #function
0134 __fa526_setup:
0135     /* On return of this routine, r0 must carry correct flags for CFG register */
0136     mov r0, #0
0137     mcr p15, 0, r0, c7, c7      @ invalidate I,D caches on v4
0138     mcr p15, 0, r0, c7, c10, 4      @ drain write buffer on v4
0139 #ifdef CONFIG_MMU
0140     mcr p15, 0, r0, c8, c7      @ invalidate I,D TLBs on v4
0141 #endif
0142     mcr p15, 0, r0, c7, c5, 5       @ invalidate IScratchpad RAM
0143
0144     mov r0, #1
0145     mcr p15, 0, r0, c1, c1, 0       @ turn-on ECR
0146
0147     mov r0, #0
0148     mcr p15, 0, r0, c7, c5, 6       @ invalidate BTB All
0149     mcr p15, 0, r0, c7, c10, 4      @ data write barrier
0150     mcr p15, 0, r0, c7, c5, 4       @ prefetch flush
0151
0152     mov r0, #0x1f           @ Domains 0, 1 = manager, 2 = client
0153     mcr p15, 0, r0, c3, c0      @ load domain access register
0154
0155     mrc p15, 0, r0, c1, c0      @ get control register v4
0156     ldr r5, fa526_cr1_clear
0157     bic r0, r0, r5
0158     ldr r5, fa526_cr1_set
0159     orr r0, r0, r5
0160     ret lr
0161     .size   __fa526_setup, . - __fa526_setup
0162
0163     /*
0164      * .RVI ZFRS BLDP WCAM
0165      * ..11 1001 .111 1101
0166      *
0167      */
0168     .type   fa526_cr1_clear, #object
0169     .type   fa526_cr1_set, #object
0170 fa526_cr1_clear:
0171     .word   0x3f3f
0172 fa526_cr1_set:
0173     .word   0x397D
0174
0175     __INITDATA
0176
0177     @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
0178     define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
0179
0180     .section ".rodata"
0181
0182     string  cpu_arch_name, "armv4"
0183     string  cpu_elf_name, "v4"
0184     string  cpu_fa526_name, "FA526"
0185
0186     .align
0187
0188     .section ".proc.info.init", "a"
0189
0190     .type   __fa526_proc_info,#object
0191 __fa526_proc_info:
0192     .long   0x66015261
0193     .long   0xff01fff1
0194     .long   PMD_TYPE_SECT | \
0195         PMD_SECT_BUFFERABLE | \
0196         PMD_SECT_CACHEABLE | \
0197         PMD_BIT4 | \
0198         PMD_SECT_AP_WRITE | \
0199         PMD_SECT_AP_READ
0200     .long   PMD_TYPE_SECT | \
0201         PMD_BIT4 | \
0202         PMD_SECT_AP_WRITE | \
0203         PMD_SECT_AP_READ
0204     initfn  __fa526_setup, __fa526_proc_info
0205     .long   cpu_arch_name
0206     .long   cpu_elf_name
0207     .long   HWCAP_SWP | HWCAP_HALF
0208     .long   cpu_fa526_name
0209     .long   fa526_processor_functions
0210     .long   fa_tlb_fns
0211     .long   fa_user_fns
0212     .long   fa_cache_fns
0213     .size   __fa526_proc_info, . - __fa526_proc_info