arm/mm/proc-arm920.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
0004  *
0005  *  Copyright (C) 1999,2000 ARM Limited
0006  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
0007  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
0008  *
0009  * These are the low level assembler for performing cache and TLB
0010  * functions on the arm920.
0011  *
0012  *  CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
0013  */
0014 #include <linux/linkage.h>
0015 #include <linux/init.h>
0016 #include <linux/pgtable.h>
0017 #include <asm/assembler.h>
0018 #include <asm/hwcap.h>
0019 #include <asm/pgtable-hwdef.h>
0020 #include <asm/page.h>
0021 #include <asm/ptrace.h>
0022 #include "proc-macros.S"
0023
0024 /*
0025  * The size of one data cache line.
0026  */
0027 #define CACHE_DLINESIZE 32
0028
0029 /*
0030  * The number of data cache segments.
0031  */
0032 #define CACHE_DSEGMENTS 8
0033
0034 /*
0035  * The number of lines in a cache segment.
0036  */
0037 #define CACHE_DENTRIES  64
0038
0039 /*
0040  * This is the size at which it becomes more efficient to
0041  * clean the whole cache, rather than using the individual
0042  * cache line maintenance instructions.
0043  */
0044 #define CACHE_DLIMIT    65536
0045
0046
0047     .text
0048 /*
0049  * cpu_arm920_proc_init()
0050  */
0051 ENTRY(cpu_arm920_proc_init)
0052     ret lr
0053
0054 /*
0055  * cpu_arm920_proc_fin()
0056  */
0057 ENTRY(cpu_arm920_proc_fin)
0058     mrc p15, 0, r0, c1, c0, 0       @ ctrl register
0059     bic r0, r0, #0x1000         @ ...i............
0060     bic r0, r0, #0x000e         @ ............wca.
0061     mcr p15, 0, r0, c1, c0, 0       @ disable caches
0062     ret lr
0063
0064 /*
0065  * cpu_arm920_reset(loc)
0066  *
0067  * Perform a soft reset of the system.  Put the CPU into the
0068  * same state as it would be if it had been reset, and branch
0069  * to what would be the reset vector.
0070  *
0071  * loc: location to jump to for soft reset
0072  */
0073     .align  5
0074     .pushsection    .idmap.text, "ax"
0075 ENTRY(cpu_arm920_reset)
0076     mov ip, #0
0077     mcr p15, 0, ip, c7, c7, 0       @ invalidate I,D caches
0078     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0079 #ifdef CONFIG_MMU
0080     mcr p15, 0, ip, c8, c7, 0       @ invalidate I & D TLBs
0081 #endif
0082     mrc p15, 0, ip, c1, c0, 0       @ ctrl register
0083     bic ip, ip, #0x000f         @ ............wcam
0084     bic ip, ip, #0x1100         @ ...i...s........
0085     mcr p15, 0, ip, c1, c0, 0       @ ctrl register
0086     ret r0
0087 ENDPROC(cpu_arm920_reset)
0088     .popsection
0089
0090 /*
0091  * cpu_arm920_do_idle()
0092  */
0093     .align  5
0094 ENTRY(cpu_arm920_do_idle)
0095     mcr p15, 0, r0, c7, c0, 4       @ Wait for interrupt
0096     ret lr
0097
0098
0099 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
0100
0101 /*
0102  *  flush_icache_all()
0103  *
0104  *  Unconditionally clean and invalidate the entire icache.
0105  */
0106 ENTRY(arm920_flush_icache_all)
0107     mov r0, #0
0108     mcr p15, 0, r0, c7, c5, 0       @ invalidate I cache
0109     ret lr
0110 ENDPROC(arm920_flush_icache_all)
0111
0112 /*
0113  *  flush_user_cache_all()
0114  *
0115  *  Invalidate all cache entries in a particular address
0116  *  space.
0117  */
0118 ENTRY(arm920_flush_user_cache_all)
0119     /* FALLTHROUGH */
0120
0121 /*
0122  *  flush_kern_cache_all()
0123  *
0124  *  Clean and invalidate the entire cache.
0125  */
0126 ENTRY(arm920_flush_kern_cache_all)
0127     mov r2, #VM_EXEC
0128     mov ip, #0
0129 __flush_whole_cache:
0130     mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
0131 1:  orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
0132 2:  mcr p15, 0, r3, c7, c14, 2      @ clean+invalidate D index
0133     subs    r3, r3, #1 << 26
0134     bcs 2b              @ entries 63 to 0
0135     subs    r1, r1, #1 << 5
0136     bcs 1b              @ segments 7 to 0
0137     tst r2, #VM_EXEC
0138     mcrne   p15, 0, ip, c7, c5, 0       @ invalidate I cache
0139     mcrne   p15, 0, ip, c7, c10, 4      @ drain WB
0140     ret lr
0141
0142 /*
0143  *  flush_user_cache_range(start, end, flags)
0144  *
0145  *  Invalidate a range of cache entries in the specified
0146  *  address space.
0147  *
0148  *  - start - start address (inclusive)
0149  *  - end   - end address (exclusive)
0150  *  - flags - vm_flags for address space
0151  */
0152 ENTRY(arm920_flush_user_cache_range)
0153     mov ip, #0
0154     sub r3, r1, r0          @ calculate total size
0155     cmp r3, #CACHE_DLIMIT
0156     bhs __flush_whole_cache
0157
0158 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0159     tst r2, #VM_EXEC
0160     mcrne   p15, 0, r0, c7, c5, 1       @ invalidate I entry
0161     add r0, r0, #CACHE_DLINESIZE
0162     cmp r0, r1
0163     blo 1b
0164     tst r2, #VM_EXEC
0165     mcrne   p15, 0, ip, c7, c10, 4      @ drain WB
0166     ret lr
0167
0168 /*
0169  *  coherent_kern_range(start, end)
0170  *
0171  *  Ensure coherency between the Icache and the Dcache in the
0172  *  region described by start, end.  If you have non-snooping
0173  *  Harvard caches, you need to implement this function.
0174  *
0175  *  - start - virtual start address
0176  *  - end   - virtual end address
0177  */
0178 ENTRY(arm920_coherent_kern_range)
0179     /* FALLTHROUGH */
0180
0181 /*
0182  *  coherent_user_range(start, end)
0183  *
0184  *  Ensure coherency between the Icache and the Dcache in the
0185  *  region described by start, end.  If you have non-snooping
0186  *  Harvard caches, you need to implement this function.
0187  *
0188  *  - start - virtual start address
0189  *  - end   - virtual end address
0190  */
0191 ENTRY(arm920_coherent_user_range)
0192     bic r0, r0, #CACHE_DLINESIZE - 1
0193 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0194     mcr p15, 0, r0, c7, c5, 1       @ invalidate I entry
0195     add r0, r0, #CACHE_DLINESIZE
0196     cmp r0, r1
0197     blo 1b
0198     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0199     mov r0, #0
0200     ret lr
0201
0202 /*
0203  *  flush_kern_dcache_area(void *addr, size_t size)
0204  *
0205  *  Ensure no D cache aliasing occurs, either with itself or
0206  *  the I cache
0207  *
0208  *  - addr  - kernel address
0209  *  - size  - region size
0210  */
0211 ENTRY(arm920_flush_kern_dcache_area)
0212     add r1, r0, r1
0213 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0214     add r0, r0, #CACHE_DLINESIZE
0215     cmp r0, r1
0216     blo 1b
0217     mov r0, #0
0218     mcr p15, 0, r0, c7, c5, 0       @ invalidate I cache
0219     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0220     ret lr
0221
0222 /*
0223  *  dma_inv_range(start, end)
0224  *
0225  *  Invalidate (discard) the specified virtual address range.
0226  *  May not write back any entries.  If 'start' or 'end'
0227  *  are not cache line aligned, those lines must be written
0228  *  back.
0229  *
0230  *  - start - virtual start address
0231  *  - end   - virtual end address
0232  *
0233  * (same as v4wb)
0234  */
0235 arm920_dma_inv_range:
0236     tst r0, #CACHE_DLINESIZE - 1
0237     bic r0, r0, #CACHE_DLINESIZE - 1
0238     mcrne   p15, 0, r0, c7, c10, 1      @ clean D entry
0239     tst r1, #CACHE_DLINESIZE - 1
0240     mcrne   p15, 0, r1, c7, c10, 1      @ clean D entry
0241 1:  mcr p15, 0, r0, c7, c6, 1       @ invalidate D entry
0242     add r0, r0, #CACHE_DLINESIZE
0243     cmp r0, r1
0244     blo 1b
0245     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0246     ret lr
0247
0248 /*
0249  *  dma_clean_range(start, end)
0250  *
0251  *  Clean the specified virtual address range.
0252  *
0253  *  - start - virtual start address
0254  *  - end   - virtual end address
0255  *
0256  * (same as v4wb)
0257  */
0258 arm920_dma_clean_range:
0259     bic r0, r0, #CACHE_DLINESIZE - 1
0260 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0261     add r0, r0, #CACHE_DLINESIZE
0262     cmp r0, r1
0263     blo 1b
0264     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0265     ret lr
0266
0267 /*
0268  *  dma_flush_range(start, end)
0269  *
0270  *  Clean and invalidate the specified virtual address range.
0271  *
0272  *  - start - virtual start address
0273  *  - end   - virtual end address
0274  */
0275 ENTRY(arm920_dma_flush_range)
0276     bic r0, r0, #CACHE_DLINESIZE - 1
0277 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0278     add r0, r0, #CACHE_DLINESIZE
0279     cmp r0, r1
0280     blo 1b
0281     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0282     ret lr
0283
0284 /*
0285  *  dma_map_area(start, size, dir)
0286  *  - start - kernel virtual start address
0287  *  - size  - size of region
0288  *  - dir   - DMA direction
0289  */
0290 ENTRY(arm920_dma_map_area)
0291     add r1, r1, r0
0292     cmp r2, #DMA_TO_DEVICE
0293     beq arm920_dma_clean_range
0294     bcs arm920_dma_inv_range
0295     b   arm920_dma_flush_range
0296 ENDPROC(arm920_dma_map_area)
0297
0298 /*
0299  *  dma_unmap_area(start, size, dir)
0300  *  - start - kernel virtual start address
0301  *  - size  - size of region
0302  *  - dir   - DMA direction
0303  */
0304 ENTRY(arm920_dma_unmap_area)
0305     ret lr
0306 ENDPROC(arm920_dma_unmap_area)
0307
0308     .globl  arm920_flush_kern_cache_louis
0309     .equ    arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all
0310
0311     @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
0312     define_cache_functions arm920
0313 #endif
0314
0315
0316 ENTRY(cpu_arm920_dcache_clean_area)
0317 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0318     add r0, r0, #CACHE_DLINESIZE
0319     subs    r1, r1, #CACHE_DLINESIZE
0320     bhi 1b
0321     ret lr
0322
0323 /* =============================== PageTable ============================== */
0324
0325 /*
0326  * cpu_arm920_switch_mm(pgd)
0327  *
0328  * Set the translation base pointer to be as described by pgd.
0329  *
0330  * pgd: new page tables
0331  */
0332     .align  5
0333 ENTRY(cpu_arm920_switch_mm)
0334 #ifdef CONFIG_MMU
0335     mov ip, #0
0336 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
0337     mcr p15, 0, ip, c7, c6, 0       @ invalidate D cache
0338 #else
0339 @ && 'Clean & Invalidate whole DCache'
0340 @ && Re-written to use Index Ops.
0341 @ && Uses registers r1, r3 and ip
0342
0343     mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
0344 1:  orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
0345 2:  mcr p15, 0, r3, c7, c14, 2      @ clean & invalidate D index
0346     subs    r3, r3, #1 << 26
0347     bcs 2b              @ entries 63 to 0
0348     subs    r1, r1, #1 << 5
0349     bcs 1b              @ segments 7 to 0
0350 #endif
0351     mcr p15, 0, ip, c7, c5, 0       @ invalidate I cache
0352     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0353     mcr p15, 0, r0, c2, c0, 0       @ load page table pointer
0354     mcr p15, 0, ip, c8, c7, 0       @ invalidate I & D TLBs
0355 #endif
0356     ret lr
0357
0358 /*
0359  * cpu_arm920_set_pte(ptep, pte, ext)
0360  *
0361  * Set a PTE and flush it out
0362  */
0363     .align  5
0364 ENTRY(cpu_arm920_set_pte_ext)
0365 #ifdef CONFIG_MMU
0366     armv3_set_pte_ext
0367     mov r0, r0
0368     mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0369     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0370 #endif
0371     ret lr
0372
0373 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
0374 .globl  cpu_arm920_suspend_size
0375 .equ    cpu_arm920_suspend_size, 4 * 3
0376 #ifdef CONFIG_ARM_CPU_SUSPEND
0377 ENTRY(cpu_arm920_do_suspend)
0378     stmfd   sp!, {r4 - r6, lr}
0379     mrc p15, 0, r4, c13, c0, 0  @ PID
0380     mrc p15, 0, r5, c3, c0, 0   @ Domain ID
0381     mrc p15, 0, r6, c1, c0, 0   @ Control register
0382     stmia   r0, {r4 - r6}
0383     ldmfd   sp!, {r4 - r6, pc}
0384 ENDPROC(cpu_arm920_do_suspend)
0385
0386 ENTRY(cpu_arm920_do_resume)
0387     mov ip, #0
0388     mcr p15, 0, ip, c8, c7, 0   @ invalidate I+D TLBs
0389     mcr p15, 0, ip, c7, c7, 0   @ invalidate I+D caches
0390     ldmia   r0, {r4 - r6}
0391     mcr p15, 0, r4, c13, c0, 0  @ PID
0392     mcr p15, 0, r5, c3, c0, 0   @ Domain ID
0393     mcr p15, 0, r1, c2, c0, 0   @ TTB address
0394     mov r0, r6          @ control register
0395     b   cpu_resume_mmu
0396 ENDPROC(cpu_arm920_do_resume)
0397 #endif
0398
0399     .type   __arm920_setup, #function
0400 __arm920_setup:
0401     mov r0, #0
0402     mcr p15, 0, r0, c7, c7      @ invalidate I,D caches on v4
0403     mcr p15, 0, r0, c7, c10, 4      @ drain write buffer on v4
0404 #ifdef CONFIG_MMU
0405     mcr p15, 0, r0, c8, c7      @ invalidate I,D TLBs on v4
0406 #endif
0407     adr r5, arm920_crval
0408     ldmia   r5, {r5, r6}
0409     mrc p15, 0, r0, c1, c0      @ get control register v4
0410     bic r0, r0, r5
0411     orr r0, r0, r6
0412     ret lr
0413     .size   __arm920_setup, . - __arm920_setup
0414
0415     /*
0416      *  R
0417      * .RVI ZFRS BLDP WCAM
0418      * ..11 0001 ..11 0101
0419      *
0420      */
0421     .type   arm920_crval, #object
0422 arm920_crval:
0423     crval   clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
0424
0425     __INITDATA
0426     @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
0427     define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1
0428
0429     .section ".rodata"
0430
0431     string  cpu_arch_name, "armv4t"
0432     string  cpu_elf_name, "v4"
0433     string  cpu_arm920_name, "ARM920T"
0434
0435     .align
0436
0437     .section ".proc.info.init", "a"
0438
0439     .type   __arm920_proc_info,#object
0440 __arm920_proc_info:
0441     .long   0x41009200
0442     .long   0xff00fff0
0443     .long   PMD_TYPE_SECT | \
0444         PMD_SECT_BUFFERABLE | \
0445         PMD_SECT_CACHEABLE | \
0446         PMD_BIT4 | \
0447         PMD_SECT_AP_WRITE | \
0448         PMD_SECT_AP_READ
0449     .long   PMD_TYPE_SECT | \
0450         PMD_BIT4 | \
0451         PMD_SECT_AP_WRITE | \
0452         PMD_SECT_AP_READ
0453     initfn  __arm920_setup, __arm920_proc_info
0454     .long   cpu_arch_name
0455     .long   cpu_elf_name
0456     .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
0457     .long   cpu_arm920_name
0458     .long   arm920_processor_functions
0459     .long   v4wbi_tlb_fns
0460     .long   v4wb_user_fns
0461 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
0462     .long   arm920_cache_fns
0463 #else
0464     .long   v4wt_cache_fns
0465 #endif
0466     .size   __arm920_proc_info, . - __arm920_proc_info