arm/mm/proc-arm740.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/arch/arm/mm/arm740.S: utility functions for ARM740
0004  *
0005  *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
0006  */
0007 #include <linux/linkage.h>
0008 #include <linux/init.h>
0009 #include <linux/pgtable.h>
0010 #include <asm/assembler.h>
0011 #include <asm/asm-offsets.h>
0012 #include <asm/hwcap.h>
0013 #include <asm/pgtable-hwdef.h>
0014 #include <asm/ptrace.h>
0015
0016 #include "proc-macros.S"
0017
0018     .text
0019 /*
0020  * cpu_arm740_proc_init()
0021  * cpu_arm740_do_idle()
0022  * cpu_arm740_dcache_clean_area()
0023  * cpu_arm740_switch_mm()
0024  *
0025  * These are not required.
0026  */
0027 ENTRY(cpu_arm740_proc_init)
0028 ENTRY(cpu_arm740_do_idle)
0029 ENTRY(cpu_arm740_dcache_clean_area)
0030 ENTRY(cpu_arm740_switch_mm)
0031     ret lr
0032
0033 /*
0034  * cpu_arm740_proc_fin()
0035  */
0036 ENTRY(cpu_arm740_proc_fin)
0037     mrc p15, 0, r0, c1, c0, 0
0038     bic r0, r0, #0x3f000000     @ bank/f/lock/s
0039     bic r0, r0, #0x0000000c     @ w-buffer/cache
0040     mcr p15, 0, r0, c1, c0, 0       @ disable caches
0041     ret lr
0042
0043 /*
0044  * cpu_arm740_reset(loc)
0045  * Params  : r0 = address to jump to
0046  * Notes   : This sets up everything for a reset
0047  */
0048     .pushsection    .idmap.text, "ax"
0049 ENTRY(cpu_arm740_reset)
0050     mov ip, #0
0051     mcr p15, 0, ip, c7, c0, 0       @ invalidate cache
0052     mrc p15, 0, ip, c1, c0, 0       @ get ctrl register
0053     bic ip, ip, #0x0000000c     @ ............wc..
0054     mcr p15, 0, ip, c1, c0, 0       @ ctrl register
0055     ret r0
0056 ENDPROC(cpu_arm740_reset)
0057     .popsection
0058
0059     .type   __arm740_setup, #function
0060 __arm740_setup:
0061     mov r0, #0
0062     mcr p15, 0, r0, c7, c0, 0       @ invalidate caches
0063
0064     mcr p15, 0, r0, c6, c3      @ disable area 3~7
0065     mcr p15, 0, r0, c6, c4
0066     mcr p15, 0, r0, c6, c5
0067     mcr p15, 0, r0, c6, c6
0068     mcr p15, 0, r0, c6, c7
0069
0070     mov r0, #0x0000003F         @ base = 0, size = 4GB
0071     mcr p15, 0, r0, c6, c0      @ set area 0, default
0072
0073     ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
0074     ldr r3, =(CONFIG_DRAM_SIZE >> 12)   @ size of RAM (must be >= 4KB)
0075     mov r4, #10             @ 11 is the minimum (4KB)
0076 1:  add r4, r4, #1          @ area size *= 2
0077     movs    r3, r3, lsr #1
0078     bne 1b              @ count not zero r-shift
0079     orr r0, r0, r4, lsl #1      @ the area register value
0080     orr r0, r0, #1          @ set enable bit
0081     mcr p15, 0, r0, c6, c1      @ set area 1, RAM
0082
0083     ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
0084     ldr r3, =(CONFIG_FLASH_SIZE >> 12)  @ size of FLASH (must be >= 4KB)
0085     cmp r3, #0
0086     moveq   r0, #0
0087     beq 2f
0088     mov r4, #10             @ 11 is the minimum (4KB)
0089 1:  add r4, r4, #1          @ area size *= 2
0090     movs    r3, r3, lsr #1
0091     bne 1b              @ count not zero r-shift
0092     orr r0, r0, r4, lsl #1      @ the area register value
0093     orr r0, r0, #1          @ set enable bit
0094 2:  mcr p15, 0, r0, c6, c2      @ set area 2, ROM/FLASH
0095
0096     mov r0, #0x06
0097     mcr p15, 0, r0, c2, c0      @ Region 1&2 cacheable
0098 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
0099     mov r0, #0x00           @ disable whole write buffer
0100 #else
0101     mov r0, #0x02           @ Region 1 write bufferred
0102 #endif
0103     mcr p15, 0, r0, c3, c0
0104
0105     mov r0, #0x10000
0106     sub r0, r0, #1          @ r0 = 0xffff
0107     mcr p15, 0, r0, c5, c0      @ all read/write access
0108
0109     mrc p15, 0, r0, c1, c0      @ get control register
0110     bic r0, r0, #0x3F000000     @ set to standard caching mode
0111                         @ need some benchmark
0112     orr r0, r0, #0x0000000d     @ MPU/Cache/WB
0113
0114     ret lr
0115
0116     .size   __arm740_setup, . - __arm740_setup
0117
0118     __INITDATA
0119
0120     @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
0121     define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1
0122
0123     .section ".rodata"
0124
0125     string  cpu_arch_name, "armv4"
0126     string  cpu_elf_name, "v4"
0127     string  cpu_arm740_name, "ARM740T"
0128
0129     .align
0130
0131     .section ".proc.info.init", "a"
0132     .type   __arm740_proc_info,#object
0133 __arm740_proc_info:
0134     .long   0x41807400
0135     .long   0xfffffff0
0136     .long   0
0137     .long   0
0138     initfn  __arm740_setup, __arm740_proc_info
0139     .long   cpu_arch_name
0140     .long   cpu_elf_name
0141     .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT
0142     .long   cpu_arm740_name
0143     .long   arm740_processor_functions
0144     .long   0
0145     .long   0
0146     .long   v4_cache_fns            @ cache model
0147     .size   __arm740_proc_info, . - __arm740_proc_info