arm/mm/proc-arm720.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
0004  *
0005  *  Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
0006  *                     Rob Scott (rscott@mtrob.fdns.net)
0007  *  Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
0008  *  hacked for non-paged-MM by Hyok S. Choi, 2004.
0009  *
0010  * These are the low level assembler for performing cache and TLB
0011  * functions on the ARM720T.  The ARM720T has a writethrough IDC
0012  * cache, so we don't need to clean it.
0013  *
0014  *  Changelog:
0015  *   05-09-2000 SJH Created by moving 720 specific functions
0016  *          out of 'proc-arm6,7.S' per RMK discussion
0017  *   07-25-2000 SJH Added idle function.
0018  *   08-25-2000 DBS Updated for integration of ARM Ltd version.
0019  *   04-20-2004 HSC modified for non-paged memory management mode.
0020  */
0021 #include <linux/linkage.h>
0022 #include <linux/init.h>
0023 #include <linux/pgtable.h>
0024 #include <asm/assembler.h>
0025 #include <asm/asm-offsets.h>
0026 #include <asm/hwcap.h>
0027 #include <asm/pgtable-hwdef.h>
0028 #include <asm/ptrace.h>
0029
0030 #include "proc-macros.S"
0031
0032 /*
0033  * Function: arm720_proc_init (void)
0034  *     : arm720_proc_fin (void)
0035  *
0036  * Notes   : This processor does not require these
0037  */
0038 ENTRY(cpu_arm720_dcache_clean_area)
0039 ENTRY(cpu_arm720_proc_init)
0040         ret lr
0041
0042 ENTRY(cpu_arm720_proc_fin)
0043         mrc p15, 0, r0, c1, c0, 0
0044         bic r0, r0, #0x1000         @ ...i............
0045         bic r0, r0, #0x000e         @ ............wca.
0046         mcr p15, 0, r0, c1, c0, 0       @ disable caches
0047         ret lr
0048
0049 /*
0050  * Function: arm720_proc_do_idle(void)
0051  * Params  : r0 = unused
0052  * Purpose : put the processor in proper idle mode
0053  */
0054 ENTRY(cpu_arm720_do_idle)
0055         ret lr
0056
0057 /*
0058  * Function: arm720_switch_mm(unsigned long pgd_phys)
0059  * Params  : pgd_phys   Physical address of page table
0060  * Purpose : Perform a task switch, saving the old process' state and restoring
0061  *       the new.
0062  */
0063 ENTRY(cpu_arm720_switch_mm)
0064 #ifdef CONFIG_MMU
0065         mov r1, #0
0066         mcr p15, 0, r1, c7, c7, 0       @ invalidate cache
0067         mcr p15, 0, r0, c2, c0, 0       @ update page table ptr
0068         mcr p15, 0, r1, c8, c7, 0       @ flush TLB (v4)
0069 #endif
0070         ret lr
0071
0072 /*
0073  * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
0074  * Params  : r0 = Address to set
0075  *     : r1 = value to set
0076  * Purpose : Set a PTE and flush it out of any WB cache
0077  */
0078     .align  5
0079 ENTRY(cpu_arm720_set_pte_ext)
0080 #ifdef CONFIG_MMU
0081     armv3_set_pte_ext wc_disable=0
0082 #endif
0083     ret lr
0084
0085 /*
0086  * Function: arm720_reset
0087  * Params  : r0 = address to jump to
0088  * Notes   : This sets up everything for a reset
0089  */
0090         .pushsection    .idmap.text, "ax"
0091 ENTRY(cpu_arm720_reset)
0092         mov ip, #0
0093         mcr p15, 0, ip, c7, c7, 0       @ invalidate cache
0094 #ifdef CONFIG_MMU
0095         mcr p15, 0, ip, c8, c7, 0       @ flush TLB (v4)
0096 #endif
0097         mrc p15, 0, ip, c1, c0, 0       @ get ctrl register
0098         bic ip, ip, #0x000f         @ ............wcam
0099         bic ip, ip, #0x2100         @ ..v....s........
0100         mcr p15, 0, ip, c1, c0, 0       @ ctrl register
0101         ret r0
0102 ENDPROC(cpu_arm720_reset)
0103         .popsection
0104
0105     .type   __arm710_setup, #function
0106 __arm710_setup:
0107     mov r0, #0
0108     mcr p15, 0, r0, c7, c7, 0       @ invalidate caches
0109 #ifdef CONFIG_MMU
0110     mcr p15, 0, r0, c8, c7, 0       @ flush TLB (v4)
0111 #endif
0112     mrc p15, 0, r0, c1, c0      @ get control register
0113     ldr r5, arm710_cr1_clear
0114     bic r0, r0, r5
0115     ldr r5, arm710_cr1_set
0116     orr r0, r0, r5
0117     ret lr              @ __ret (head.S)
0118     .size   __arm710_setup, . - __arm710_setup
0119
0120     /*
0121      *  R
0122      * .RVI ZFRS BLDP WCAM
0123      * .... 0001 ..11 1101
0124      *
0125      */
0126     .type   arm710_cr1_clear, #object
0127     .type   arm710_cr1_set, #object
0128 arm710_cr1_clear:
0129     .word   0x0f3f
0130 arm710_cr1_set:
0131     .word   0x013d
0132
0133     .type   __arm720_setup, #function
0134 __arm720_setup:
0135     mov r0, #0
0136     mcr p15, 0, r0, c7, c7, 0       @ invalidate caches
0137 #ifdef CONFIG_MMU
0138     mcr p15, 0, r0, c8, c7, 0       @ flush TLB (v4)
0139 #endif
0140     adr r5, arm720_crval
0141     ldmia   r5, {r5, r6}
0142     mrc p15, 0, r0, c1, c0      @ get control register
0143     bic r0, r0, r5
0144     orr r0, r0, r6
0145     ret lr              @ __ret (head.S)
0146     .size   __arm720_setup, . - __arm720_setup
0147
0148     /*
0149      *  R
0150      * .RVI ZFRS BLDP WCAM
0151      * ..1. 1001 ..11 1101
0152      *
0153      */
0154     .type   arm720_crval, #object
0155 arm720_crval:
0156     crval   clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
0157
0158         __INITDATA
0159     @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
0160     define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort
0161
0162         .section ".rodata"
0163
0164     string  cpu_arch_name, "armv4t"
0165     string  cpu_elf_name, "v4"
0166     string  cpu_arm710_name, "ARM710T"
0167     string  cpu_arm720_name, "ARM720T"
0168
0169         .align
0170
0171 /*
0172  * See <asm/procinfo.h> for a definition of this structure.
0173  */
0174
0175         .section ".proc.info.init", "a"
0176
0177 .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
0178         .type   __\name\()_proc_info,#object
0179 __\name\()_proc_info:
0180         .long   \cpu_val
0181         .long   \cpu_mask
0182         .long   PMD_TYPE_SECT | \
0183             PMD_SECT_BUFFERABLE | \
0184             PMD_SECT_CACHEABLE | \
0185             PMD_BIT4 | \
0186             PMD_SECT_AP_WRITE | \
0187             PMD_SECT_AP_READ
0188         .long   PMD_TYPE_SECT | \
0189             PMD_BIT4 | \
0190             PMD_SECT_AP_WRITE | \
0191             PMD_SECT_AP_READ
0192         initfn  \cpu_flush, __\name\()_proc_info    @ cpu_flush
0193         .long   cpu_arch_name               @ arch_name
0194         .long   cpu_elf_name                @ elf_name
0195         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB    @ elf_hwcap
0196         .long   \cpu_name
0197         .long   arm720_processor_functions
0198         .long   v4_tlb_fns
0199         .long   v4wt_user_fns
0200         .long   v4_cache_fns
0201         .size   __\name\()_proc_info, . - __\name\()_proc_info
0202 .endm
0203
0204     arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
0205     arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup