arm/mm/proc-arm1026.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
0004  *
0005  *  Copyright (C) 2000 ARM Limited
0006  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
0007  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
0008  *
0009  * These are the low level assembler for performing cache and TLB
0010  * functions on the ARM1026EJ-S.
0011  */
0012 #include <linux/linkage.h>
0013 #include <linux/init.h>
0014 #include <linux/pgtable.h>
0015 #include <asm/assembler.h>
0016 #include <asm/asm-offsets.h>
0017 #include <asm/hwcap.h>
0018 #include <asm/pgtable-hwdef.h>
0019 #include <asm/ptrace.h>
0020
0021 #include "proc-macros.S"
0022
0023 /*
0024  * This is the maximum size of an area which will be invalidated
0025  * using the single invalidate entry instructions.  Anything larger
0026  * than this, and we go for the whole cache.
0027  *
0028  * This value should be chosen such that we choose the cheapest
0029  * alternative.
0030  */
0031 #define MAX_AREA_SIZE   32768
0032
0033 /*
0034  * The size of one data cache line.
0035  */
0036 #define CACHE_DLINESIZE 32
0037
0038 /*
0039  * The number of data cache segments.
0040  */
0041 #define CACHE_DSEGMENTS 16
0042
0043 /*
0044  * The number of lines in a cache segment.
0045  */
0046 #define CACHE_DENTRIES  64
0047
0048 /*
0049  * This is the size at which it becomes more efficient to
0050  * clean the whole cache, rather than using the individual
0051  * cache line maintenance instructions.
0052  */
0053 #define CACHE_DLIMIT    32768
0054
0055     .text
0056 /*
0057  * cpu_arm1026_proc_init()
0058  */
0059 ENTRY(cpu_arm1026_proc_init)
0060     ret lr
0061
0062 /*
0063  * cpu_arm1026_proc_fin()
0064  */
0065 ENTRY(cpu_arm1026_proc_fin)
0066     mrc p15, 0, r0, c1, c0, 0       @ ctrl register
0067     bic r0, r0, #0x1000         @ ...i............
0068     bic r0, r0, #0x000e         @ ............wca.
0069     mcr p15, 0, r0, c1, c0, 0       @ disable caches
0070     ret lr
0071
0072 /*
0073  * cpu_arm1026_reset(loc)
0074  *
0075  * Perform a soft reset of the system.  Put the CPU into the
0076  * same state as it would be if it had been reset, and branch
0077  * to what would be the reset vector.
0078  *
0079  * loc: location to jump to for soft reset
0080  */
0081     .align  5
0082     .pushsection    .idmap.text, "ax"
0083 ENTRY(cpu_arm1026_reset)
0084     mov ip, #0
0085     mcr p15, 0, ip, c7, c7, 0       @ invalidate I,D caches
0086     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0087 #ifdef CONFIG_MMU
0088     mcr p15, 0, ip, c8, c7, 0       @ invalidate I & D TLBs
0089 #endif
0090     mrc p15, 0, ip, c1, c0, 0       @ ctrl register
0091     bic ip, ip, #0x000f         @ ............wcam
0092     bic ip, ip, #0x1100         @ ...i...s........
0093     mcr p15, 0, ip, c1, c0, 0       @ ctrl register
0094     ret r0
0095 ENDPROC(cpu_arm1026_reset)
0096     .popsection
0097
0098 /*
0099  * cpu_arm1026_do_idle()
0100  */
0101     .align  5
0102 ENTRY(cpu_arm1026_do_idle)
0103     mcr p15, 0, r0, c7, c0, 4       @ Wait for interrupt
0104     ret lr
0105
0106 /* ================================= CACHE ================================ */
0107
0108     .align  5
0109
0110 /*
0111  *  flush_icache_all()
0112  *
0113  *  Unconditionally clean and invalidate the entire icache.
0114  */
0115 ENTRY(arm1026_flush_icache_all)
0116 #ifndef CONFIG_CPU_ICACHE_DISABLE
0117     mov r0, #0
0118     mcr p15, 0, r0, c7, c5, 0       @ invalidate I cache
0119 #endif
0120     ret lr
0121 ENDPROC(arm1026_flush_icache_all)
0122
0123 /*
0124  *  flush_user_cache_all()
0125  *
0126  *  Invalidate all cache entries in a particular address
0127  *  space.
0128  */
0129 ENTRY(arm1026_flush_user_cache_all)
0130     /* FALLTHROUGH */
0131 /*
0132  *  flush_kern_cache_all()
0133  *
0134  *  Clean and invalidate the entire cache.
0135  */
0136 ENTRY(arm1026_flush_kern_cache_all)
0137     mov r2, #VM_EXEC
0138     mov ip, #0
0139 __flush_whole_cache:
0140 #ifndef CONFIG_CPU_DCACHE_DISABLE
0141 1:  mrc p15, 0, APSR_nzcv, c7, c14, 3       @ test, clean, invalidate
0142     bne 1b
0143 #endif
0144     tst r2, #VM_EXEC
0145 #ifndef CONFIG_CPU_ICACHE_DISABLE
0146     mcrne   p15, 0, ip, c7, c5, 0       @ invalidate I cache
0147 #endif
0148     mcrne   p15, 0, ip, c7, c10, 4      @ drain WB
0149     ret lr
0150
0151 /*
0152  *  flush_user_cache_range(start, end, flags)
0153  *
0154  *  Invalidate a range of cache entries in the specified
0155  *  address space.
0156  *
0157  *  - start - start address (inclusive)
0158  *  - end   - end address (exclusive)
0159  *  - flags - vm_flags for this space
0160  */
0161 ENTRY(arm1026_flush_user_cache_range)
0162     mov ip, #0
0163     sub r3, r1, r0          @ calculate total size
0164     cmp r3, #CACHE_DLIMIT
0165     bhs __flush_whole_cache
0166
0167 #ifndef CONFIG_CPU_DCACHE_DISABLE
0168 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0169     add r0, r0, #CACHE_DLINESIZE
0170     cmp r0, r1
0171     blo 1b
0172 #endif
0173     tst r2, #VM_EXEC
0174 #ifndef CONFIG_CPU_ICACHE_DISABLE
0175     mcrne   p15, 0, ip, c7, c5, 0       @ invalidate I cache
0176 #endif
0177     mcrne   p15, 0, ip, c7, c10, 4      @ drain WB
0178     ret lr
0179
0180 /*
0181  *  coherent_kern_range(start, end)
0182  *
0183  *  Ensure coherency between the Icache and the Dcache in the
0184  *  region described by start.  If you have non-snooping
0185  *  Harvard caches, you need to implement this function.
0186  *
0187  *  - start - virtual start address
0188  *  - end   - virtual end address
0189  */
0190 ENTRY(arm1026_coherent_kern_range)
0191     /* FALLTHROUGH */
0192 /*
0193  *  coherent_user_range(start, end)
0194  *
0195  *  Ensure coherency between the Icache and the Dcache in the
0196  *  region described by start.  If you have non-snooping
0197  *  Harvard caches, you need to implement this function.
0198  *
0199  *  - start - virtual start address
0200  *  - end   - virtual end address
0201  */
0202 ENTRY(arm1026_coherent_user_range)
0203     mov ip, #0
0204     bic r0, r0, #CACHE_DLINESIZE - 1
0205 1:
0206 #ifndef CONFIG_CPU_DCACHE_DISABLE
0207     mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0208 #endif
0209 #ifndef CONFIG_CPU_ICACHE_DISABLE
0210     mcr p15, 0, r0, c7, c5, 1       @ invalidate I entry
0211 #endif
0212     add r0, r0, #CACHE_DLINESIZE
0213     cmp r0, r1
0214     blo 1b
0215     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0216     mov r0, #0
0217     ret lr
0218
0219 /*
0220  *  flush_kern_dcache_area(void *addr, size_t size)
0221  *
0222  *  Ensure no D cache aliasing occurs, either with itself or
0223  *  the I cache
0224  *
0225  *  - addr  - kernel address
0226  *  - size  - region size
0227  */
0228 ENTRY(arm1026_flush_kern_dcache_area)
0229     mov ip, #0
0230 #ifndef CONFIG_CPU_DCACHE_DISABLE
0231     add r1, r0, r1
0232 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0233     add r0, r0, #CACHE_DLINESIZE
0234     cmp r0, r1
0235     blo 1b
0236 #endif
0237     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0238     ret lr
0239
0240 /*
0241  *  dma_inv_range(start, end)
0242  *
0243  *  Invalidate (discard) the specified virtual address range.
0244  *  May not write back any entries.  If 'start' or 'end'
0245  *  are not cache line aligned, those lines must be written
0246  *  back.
0247  *
0248  *  - start - virtual start address
0249  *  - end   - virtual end address
0250  *
0251  * (same as v4wb)
0252  */
0253 arm1026_dma_inv_range:
0254     mov ip, #0
0255 #ifndef CONFIG_CPU_DCACHE_DISABLE
0256     tst r0, #CACHE_DLINESIZE - 1
0257     bic r0, r0, #CACHE_DLINESIZE - 1
0258     mcrne   p15, 0, r0, c7, c10, 1      @ clean D entry
0259     tst r1, #CACHE_DLINESIZE - 1
0260     mcrne   p15, 0, r1, c7, c10, 1      @ clean D entry
0261 1:  mcr p15, 0, r0, c7, c6, 1       @ invalidate D entry
0262     add r0, r0, #CACHE_DLINESIZE
0263     cmp r0, r1
0264     blo 1b
0265 #endif
0266     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0267     ret lr
0268
0269 /*
0270  *  dma_clean_range(start, end)
0271  *
0272  *  Clean the specified virtual address range.
0273  *
0274  *  - start - virtual start address
0275  *  - end   - virtual end address
0276  *
0277  * (same as v4wb)
0278  */
0279 arm1026_dma_clean_range:
0280     mov ip, #0
0281 #ifndef CONFIG_CPU_DCACHE_DISABLE
0282     bic r0, r0, #CACHE_DLINESIZE - 1
0283 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0284     add r0, r0, #CACHE_DLINESIZE
0285     cmp r0, r1
0286     blo 1b
0287 #endif
0288     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0289     ret lr
0290
0291 /*
0292  *  dma_flush_range(start, end)
0293  *
0294  *  Clean and invalidate the specified virtual address range.
0295  *
0296  *  - start - virtual start address
0297  *  - end   - virtual end address
0298  */
0299 ENTRY(arm1026_dma_flush_range)
0300     mov ip, #0
0301 #ifndef CONFIG_CPU_DCACHE_DISABLE
0302     bic r0, r0, #CACHE_DLINESIZE - 1
0303 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0304     add r0, r0, #CACHE_DLINESIZE
0305     cmp r0, r1
0306     blo 1b
0307 #endif
0308     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0309     ret lr
0310
0311 /*
0312  *  dma_map_area(start, size, dir)
0313  *  - start - kernel virtual start address
0314  *  - size  - size of region
0315  *  - dir   - DMA direction
0316  */
0317 ENTRY(arm1026_dma_map_area)
0318     add r1, r1, r0
0319     cmp r2, #DMA_TO_DEVICE
0320     beq arm1026_dma_clean_range
0321     bcs arm1026_dma_inv_range
0322     b   arm1026_dma_flush_range
0323 ENDPROC(arm1026_dma_map_area)
0324
0325 /*
0326  *  dma_unmap_area(start, size, dir)
0327  *  - start - kernel virtual start address
0328  *  - size  - size of region
0329  *  - dir   - DMA direction
0330  */
0331 ENTRY(arm1026_dma_unmap_area)
0332     ret lr
0333 ENDPROC(arm1026_dma_unmap_area)
0334
0335     .globl  arm1026_flush_kern_cache_louis
0336     .equ    arm1026_flush_kern_cache_louis, arm1026_flush_kern_cache_all
0337
0338     @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
0339     define_cache_functions arm1026
0340
0341     .align  5
0342 ENTRY(cpu_arm1026_dcache_clean_area)
0343 #ifndef CONFIG_CPU_DCACHE_DISABLE
0344     mov ip, #0
0345 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0346     add r0, r0, #CACHE_DLINESIZE
0347     subs    r1, r1, #CACHE_DLINESIZE
0348     bhi 1b
0349 #endif
0350     ret lr
0351
0352 /* =============================== PageTable ============================== */
0353
0354 /*
0355  * cpu_arm1026_switch_mm(pgd)
0356  *
0357  * Set the translation base pointer to be as described by pgd.
0358  *
0359  * pgd: new page tables
0360  */
0361     .align  5
0362 ENTRY(cpu_arm1026_switch_mm)
0363 #ifdef CONFIG_MMU
0364     mov r1, #0
0365 #ifndef CONFIG_CPU_DCACHE_DISABLE
0366 1:  mrc p15, 0, APSR_nzcv, c7, c14, 3       @ test, clean, invalidate
0367     bne 1b
0368 #endif
0369 #ifndef CONFIG_CPU_ICACHE_DISABLE
0370     mcr p15, 0, r1, c7, c5, 0       @ invalidate I cache
0371 #endif
0372     mcr p15, 0, r1, c7, c10, 4      @ drain WB
0373     mcr p15, 0, r0, c2, c0, 0       @ load page table pointer
0374     mcr p15, 0, r1, c8, c7, 0       @ invalidate I & D TLBs
0375 #endif
0376     ret lr
0377
0378 /*
0379  * cpu_arm1026_set_pte_ext(ptep, pte, ext)
0380  *
0381  * Set a PTE and flush it out
0382  */
0383     .align  5
0384 ENTRY(cpu_arm1026_set_pte_ext)
0385 #ifdef CONFIG_MMU
0386     armv3_set_pte_ext
0387     mov r0, r0
0388 #ifndef CONFIG_CPU_DCACHE_DISABLE
0389     mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0390 #endif
0391 #endif /* CONFIG_MMU */
0392     ret lr
0393
0394     .type   __arm1026_setup, #function
0395 __arm1026_setup:
0396     mov r0, #0
0397     mcr p15, 0, r0, c7, c7      @ invalidate I,D caches on v4
0398     mcr p15, 0, r0, c7, c10, 4      @ drain write buffer on v4
0399 #ifdef CONFIG_MMU
0400     mcr p15, 0, r0, c8, c7      @ invalidate I,D TLBs on v4
0401     mcr p15, 0, r4, c2, c0      @ load page table pointer
0402 #endif
0403 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
0404     mov r0, #4              @ explicitly disable writeback
0405     mcr p15, 7, r0, c15, c0, 0
0406 #endif
0407     adr r5, arm1026_crval
0408     ldmia   r5, {r5, r6}
0409     mrc p15, 0, r0, c1, c0      @ get control register v4
0410     bic r0, r0, r5
0411     orr r0, r0, r6
0412 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
0413     orr r0, r0, #0x4000         @ .R.. .... .... ....
0414 #endif
0415     ret lr
0416     .size   __arm1026_setup, . - __arm1026_setup
0417
0418     /*
0419      *  R
0420      * .RVI ZFRS BLDP WCAM
0421      * .011 1001 ..11 0101
0422      *
0423      */
0424     .type   arm1026_crval, #object
0425 arm1026_crval:
0426     crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
0427
0428     __INITDATA
0429     @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
0430     define_processor_functions arm1026, dabort=v5t_early_abort, pabort=legacy_pabort
0431
0432     .section .rodata
0433
0434     string  cpu_arch_name, "armv5tej"
0435     string  cpu_elf_name, "v5"
0436     .align
0437     string  cpu_arm1026_name, "ARM1026EJ-S"
0438     .align
0439
0440     .section ".proc.info.init", "a"
0441
0442     .type   __arm1026_proc_info,#object
0443 __arm1026_proc_info:
0444     .long   0x4106a260          @ ARM 1026EJ-S (v5TEJ)
0445     .long   0xff0ffff0
0446     .long   PMD_TYPE_SECT | \
0447         PMD_BIT4 | \
0448         PMD_SECT_AP_WRITE | \
0449         PMD_SECT_AP_READ
0450     .long   PMD_TYPE_SECT | \
0451         PMD_BIT4 | \
0452         PMD_SECT_AP_WRITE | \
0453         PMD_SECT_AP_READ
0454     initfn  __arm1026_setup, __arm1026_proc_info
0455     .long   cpu_arch_name
0456     .long   cpu_elf_name
0457     .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
0458     .long   cpu_arm1026_name
0459     .long   arm1026_processor_functions
0460     .long   v4wbi_tlb_fns
0461     .long   v4wb_user_fns
0462     .long   arm1026_cache_fns
0463     .size   __arm1026_proc_info, . - __arm1026_proc_info