arm/mm/proc-arm1020.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
0004  *
0005  *  Copyright (C) 2000 ARM Limited
0006  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
0007  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
0008  *
0009  * These are the low level assembler for performing cache and TLB
0010  * functions on the arm1020.
0011  */
0012 #include <linux/linkage.h>
0013 #include <linux/init.h>
0014 #include <linux/pgtable.h>
0015 #include <asm/assembler.h>
0016 #include <asm/asm-offsets.h>
0017 #include <asm/hwcap.h>
0018 #include <asm/pgtable-hwdef.h>
0019 #include <asm/ptrace.h>
0020
0021 #include "proc-macros.S"
0022
0023 /*
0024  * This is the maximum size of an area which will be invalidated
0025  * using the single invalidate entry instructions.  Anything larger
0026  * than this, and we go for the whole cache.
0027  *
0028  * This value should be chosen such that we choose the cheapest
0029  * alternative.
0030  */
0031 #define MAX_AREA_SIZE   32768
0032
0033 /*
0034  * The size of one data cache line.
0035  */
0036 #define CACHE_DLINESIZE 32
0037
0038 /*
0039  * The number of data cache segments.
0040  */
0041 #define CACHE_DSEGMENTS 16
0042
0043 /*
0044  * The number of lines in a cache segment.
0045  */
0046 #define CACHE_DENTRIES  64
0047
0048 /*
0049  * This is the size at which it becomes more efficient to
0050  * clean the whole cache, rather than using the individual
0051  * cache line maintenance instructions.
0052  */
0053 #define CACHE_DLIMIT    32768
0054
0055     .text
0056 /*
0057  * cpu_arm1020_proc_init()
0058  */
0059 ENTRY(cpu_arm1020_proc_init)
0060     ret lr
0061
0062 /*
0063  * cpu_arm1020_proc_fin()
0064  */
0065 ENTRY(cpu_arm1020_proc_fin)
0066     mrc p15, 0, r0, c1, c0, 0       @ ctrl register
0067     bic r0, r0, #0x1000         @ ...i............
0068     bic r0, r0, #0x000e         @ ............wca.
0069     mcr p15, 0, r0, c1, c0, 0       @ disable caches
0070     ret lr
0071
0072 /*
0073  * cpu_arm1020_reset(loc)
0074  *
0075  * Perform a soft reset of the system.  Put the CPU into the
0076  * same state as it would be if it had been reset, and branch
0077  * to what would be the reset vector.
0078  *
0079  * loc: location to jump to for soft reset
0080  */
0081     .align  5
0082     .pushsection    .idmap.text, "ax"
0083 ENTRY(cpu_arm1020_reset)
0084     mov ip, #0
0085     mcr p15, 0, ip, c7, c7, 0       @ invalidate I,D caches
0086     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0087 #ifdef CONFIG_MMU
0088     mcr p15, 0, ip, c8, c7, 0       @ invalidate I & D TLBs
0089 #endif
0090     mrc p15, 0, ip, c1, c0, 0       @ ctrl register
0091     bic ip, ip, #0x000f         @ ............wcam
0092     bic ip, ip, #0x1100         @ ...i...s........
0093     mcr p15, 0, ip, c1, c0, 0       @ ctrl register
0094     ret r0
0095 ENDPROC(cpu_arm1020_reset)
0096     .popsection
0097
0098 /*
0099  * cpu_arm1020_do_idle()
0100  */
0101     .align  5
0102 ENTRY(cpu_arm1020_do_idle)
0103     mcr p15, 0, r0, c7, c0, 4       @ Wait for interrupt
0104     ret lr
0105
0106 /* ================================= CACHE ================================ */
0107
0108     .align  5
0109
0110 /*
0111  *  flush_icache_all()
0112  *
0113  *  Unconditionally clean and invalidate the entire icache.
0114  */
0115 ENTRY(arm1020_flush_icache_all)
0116 #ifndef CONFIG_CPU_ICACHE_DISABLE
0117     mov r0, #0
0118     mcr p15, 0, r0, c7, c5, 0       @ invalidate I cache
0119 #endif
0120     ret lr
0121 ENDPROC(arm1020_flush_icache_all)
0122
0123 /*
0124  *  flush_user_cache_all()
0125  *
0126  *  Invalidate all cache entries in a particular address
0127  *  space.
0128  */
0129 ENTRY(arm1020_flush_user_cache_all)
0130     /* FALLTHROUGH */
0131 /*
0132  *  flush_kern_cache_all()
0133  *
0134  *  Clean and invalidate the entire cache.
0135  */
0136 ENTRY(arm1020_flush_kern_cache_all)
0137     mov r2, #VM_EXEC
0138     mov ip, #0
0139 __flush_whole_cache:
0140 #ifndef CONFIG_CPU_DCACHE_DISABLE
0141     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0142     mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
0143 1:  orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
0144 2:  mcr p15, 0, r3, c7, c14, 2      @ clean+invalidate D index
0145     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0146     subs    r3, r3, #1 << 26
0147     bcs 2b              @ entries 63 to 0
0148     subs    r1, r1, #1 << 5
0149     bcs 1b              @ segments 15 to 0
0150 #endif
0151     tst r2, #VM_EXEC
0152 #ifndef CONFIG_CPU_ICACHE_DISABLE
0153     mcrne   p15, 0, ip, c7, c5, 0       @ invalidate I cache
0154 #endif
0155     mcrne   p15, 0, ip, c7, c10, 4      @ drain WB
0156     ret lr
0157
0158 /*
0159  *  flush_user_cache_range(start, end, flags)
0160  *
0161  *  Invalidate a range of cache entries in the specified
0162  *  address space.
0163  *
0164  *  - start - start address (inclusive)
0165  *  - end   - end address (exclusive)
0166  *  - flags - vm_flags for this space
0167  */
0168 ENTRY(arm1020_flush_user_cache_range)
0169     mov ip, #0
0170     sub r3, r1, r0          @ calculate total size
0171     cmp r3, #CACHE_DLIMIT
0172     bhs __flush_whole_cache
0173
0174 #ifndef CONFIG_CPU_DCACHE_DISABLE
0175     mcr p15, 0, ip, c7, c10, 4
0176 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0177     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0178     add r0, r0, #CACHE_DLINESIZE
0179     cmp r0, r1
0180     blo 1b
0181 #endif
0182     tst r2, #VM_EXEC
0183 #ifndef CONFIG_CPU_ICACHE_DISABLE
0184     mcrne   p15, 0, ip, c7, c5, 0       @ invalidate I cache
0185 #endif
0186     mcrne   p15, 0, ip, c7, c10, 4      @ drain WB
0187     ret lr
0188
0189 /*
0190  *  coherent_kern_range(start, end)
0191  *
0192  *  Ensure coherency between the Icache and the Dcache in the
0193  *  region described by start.  If you have non-snooping
0194  *  Harvard caches, you need to implement this function.
0195  *
0196  *  - start - virtual start address
0197  *  - end   - virtual end address
0198  */
0199 ENTRY(arm1020_coherent_kern_range)
0200     /* FALLTRHOUGH */
0201
0202 /*
0203  *  coherent_user_range(start, end)
0204  *
0205  *  Ensure coherency between the Icache and the Dcache in the
0206  *  region described by start.  If you have non-snooping
0207  *  Harvard caches, you need to implement this function.
0208  *
0209  *  - start - virtual start address
0210  *  - end   - virtual end address
0211  */
0212 ENTRY(arm1020_coherent_user_range)
0213     mov ip, #0
0214     bic r0, r0, #CACHE_DLINESIZE - 1
0215     mcr p15, 0, ip, c7, c10, 4
0216 1:
0217 #ifndef CONFIG_CPU_DCACHE_DISABLE
0218     mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0219     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0220 #endif
0221 #ifndef CONFIG_CPU_ICACHE_DISABLE
0222     mcr p15, 0, r0, c7, c5, 1       @ invalidate I entry
0223 #endif
0224     add r0, r0, #CACHE_DLINESIZE
0225     cmp r0, r1
0226     blo 1b
0227     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0228     mov r0, #0
0229     ret lr
0230
0231 /*
0232  *  flush_kern_dcache_area(void *addr, size_t size)
0233  *
0234  *  Ensure no D cache aliasing occurs, either with itself or
0235  *  the I cache
0236  *
0237  *  - addr  - kernel address
0238  *  - size  - region size
0239  */
0240 ENTRY(arm1020_flush_kern_dcache_area)
0241     mov ip, #0
0242 #ifndef CONFIG_CPU_DCACHE_DISABLE
0243     add r1, r0, r1
0244 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0245     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0246     add r0, r0, #CACHE_DLINESIZE
0247     cmp r0, r1
0248     blo 1b
0249 #endif
0250     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0251     ret lr
0252
0253 /*
0254  *  dma_inv_range(start, end)
0255  *
0256  *  Invalidate (discard) the specified virtual address range.
0257  *  May not write back any entries.  If 'start' or 'end'
0258  *  are not cache line aligned, those lines must be written
0259  *  back.
0260  *
0261  *  - start - virtual start address
0262  *  - end   - virtual end address
0263  *
0264  * (same as v4wb)
0265  */
0266 arm1020_dma_inv_range:
0267     mov ip, #0
0268 #ifndef CONFIG_CPU_DCACHE_DISABLE
0269     tst r0, #CACHE_DLINESIZE - 1
0270     bic r0, r0, #CACHE_DLINESIZE - 1
0271     mcrne   p15, 0, ip, c7, c10, 4
0272     mcrne   p15, 0, r0, c7, c10, 1      @ clean D entry
0273     mcrne   p15, 0, ip, c7, c10, 4      @ drain WB
0274     tst r1, #CACHE_DLINESIZE - 1
0275     mcrne   p15, 0, ip, c7, c10, 4
0276     mcrne   p15, 0, r1, c7, c10, 1      @ clean D entry
0277     mcrne   p15, 0, ip, c7, c10, 4      @ drain WB
0278 1:  mcr p15, 0, r0, c7, c6, 1       @ invalidate D entry
0279     add r0, r0, #CACHE_DLINESIZE
0280     cmp r0, r1
0281     blo 1b
0282 #endif
0283     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0284     ret lr
0285
0286 /*
0287  *  dma_clean_range(start, end)
0288  *
0289  *  Clean the specified virtual address range.
0290  *
0291  *  - start - virtual start address
0292  *  - end   - virtual end address
0293  *
0294  * (same as v4wb)
0295  */
0296 arm1020_dma_clean_range:
0297     mov ip, #0
0298 #ifndef CONFIG_CPU_DCACHE_DISABLE
0299     bic r0, r0, #CACHE_DLINESIZE - 1
0300 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0301     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0302     add r0, r0, #CACHE_DLINESIZE
0303     cmp r0, r1
0304     blo 1b
0305 #endif
0306     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0307     ret lr
0308
0309 /*
0310  *  dma_flush_range(start, end)
0311  *
0312  *  Clean and invalidate the specified virtual address range.
0313  *
0314  *  - start - virtual start address
0315  *  - end   - virtual end address
0316  */
0317 ENTRY(arm1020_dma_flush_range)
0318     mov ip, #0
0319 #ifndef CONFIG_CPU_DCACHE_DISABLE
0320     bic r0, r0, #CACHE_DLINESIZE - 1
0321     mcr p15, 0, ip, c7, c10, 4
0322 1:  mcr p15, 0, r0, c7, c14, 1      @ clean+invalidate D entry
0323     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0324     add r0, r0, #CACHE_DLINESIZE
0325     cmp r0, r1
0326     blo 1b
0327 #endif
0328     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0329     ret lr
0330
0331 /*
0332  *  dma_map_area(start, size, dir)
0333  *  - start - kernel virtual start address
0334  *  - size  - size of region
0335  *  - dir   - DMA direction
0336  */
0337 ENTRY(arm1020_dma_map_area)
0338     add r1, r1, r0
0339     cmp r2, #DMA_TO_DEVICE
0340     beq arm1020_dma_clean_range
0341     bcs arm1020_dma_inv_range
0342     b   arm1020_dma_flush_range
0343 ENDPROC(arm1020_dma_map_area)
0344
0345 /*
0346  *  dma_unmap_area(start, size, dir)
0347  *  - start - kernel virtual start address
0348  *  - size  - size of region
0349  *  - dir   - DMA direction
0350  */
0351 ENTRY(arm1020_dma_unmap_area)
0352     ret lr
0353 ENDPROC(arm1020_dma_unmap_area)
0354
0355     .globl  arm1020_flush_kern_cache_louis
0356     .equ    arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all
0357
0358     @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
0359     define_cache_functions arm1020
0360
0361     .align  5
0362 ENTRY(cpu_arm1020_dcache_clean_area)
0363 #ifndef CONFIG_CPU_DCACHE_DISABLE
0364     mov ip, #0
0365 1:  mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0366     mcr p15, 0, ip, c7, c10, 4      @ drain WB
0367     add r0, r0, #CACHE_DLINESIZE
0368     subs    r1, r1, #CACHE_DLINESIZE
0369     bhi 1b
0370 #endif
0371     ret lr
0372
0373 /* =============================== PageTable ============================== */
0374
0375 /*
0376  * cpu_arm1020_switch_mm(pgd)
0377  *
0378  * Set the translation base pointer to be as described by pgd.
0379  *
0380  * pgd: new page tables
0381  */
0382     .align  5
0383 ENTRY(cpu_arm1020_switch_mm)
0384 #ifdef CONFIG_MMU
0385 #ifndef CONFIG_CPU_DCACHE_DISABLE
0386     mcr p15, 0, r3, c7, c10, 4
0387     mov r1, #0xF            @ 16 segments
0388 1:  mov r3, #0x3F           @ 64 entries
0389 2:  mov ip, r3, LSL #26         @ shift up entry
0390     orr ip, ip, r1, LSL #5      @ shift in/up index
0391     mcr p15, 0, ip, c7, c14, 2      @ Clean & Inval DCache entry
0392     mov ip, #0
0393     mcr p15, 0, ip, c7, c10, 4
0394     subs    r3, r3, #1
0395     cmp r3, #0
0396     bge 2b              @ entries 3F to 0
0397     subs    r1, r1, #1
0398     cmp r1, #0
0399     bge 1b              @ segments 15 to 0
0400
0401 #endif
0402     mov r1, #0
0403 #ifndef CONFIG_CPU_ICACHE_DISABLE
0404     mcr p15, 0, r1, c7, c5, 0       @ invalidate I cache
0405 #endif
0406     mcr p15, 0, r1, c7, c10, 4      @ drain WB
0407     mcr p15, 0, r0, c2, c0, 0       @ load page table pointer
0408     mcr p15, 0, r1, c8, c7, 0       @ invalidate I & D TLBs
0409 #endif /* CONFIG_MMU */
0410     ret lr
0411
0412 /*
0413  * cpu_arm1020_set_pte(ptep, pte)
0414  *
0415  * Set a PTE and flush it out
0416  */
0417     .align  5
0418 ENTRY(cpu_arm1020_set_pte_ext)
0419 #ifdef CONFIG_MMU
0420     armv3_set_pte_ext
0421     mov r0, r0
0422 #ifndef CONFIG_CPU_DCACHE_DISABLE
0423     mcr p15, 0, r0, c7, c10, 4
0424     mcr p15, 0, r0, c7, c10, 1      @ clean D entry
0425 #endif
0426     mcr p15, 0, r0, c7, c10, 4      @ drain WB
0427 #endif /* CONFIG_MMU */
0428     ret lr
0429
0430     .type   __arm1020_setup, #function
0431 __arm1020_setup:
0432     mov r0, #0
0433     mcr p15, 0, r0, c7, c7      @ invalidate I,D caches on v4
0434     mcr p15, 0, r0, c7, c10, 4      @ drain write buffer on v4
0435 #ifdef CONFIG_MMU
0436     mcr p15, 0, r0, c8, c7      @ invalidate I,D TLBs on v4
0437 #endif
0438
0439     adr r5, arm1020_crval
0440     ldmia   r5, {r5, r6}
0441     mrc p15, 0, r0, c1, c0      @ get control register v4
0442     bic r0, r0, r5
0443     orr r0, r0, r6
0444 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
0445     orr r0, r0, #0x4000         @ .R.. .... .... ....
0446 #endif
0447     ret lr
0448     .size   __arm1020_setup, . - __arm1020_setup
0449
0450     /*
0451      *  R
0452      * .RVI ZFRS BLDP WCAM
0453      * .011 1001 ..11 0101
0454      */
0455     .type   arm1020_crval, #object
0456 arm1020_crval:
0457     crval   clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
0458
0459     __INITDATA
0460     @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
0461     define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
0462
0463
0464     .section ".rodata"
0465
0466     string  cpu_arch_name, "armv5t"
0467     string  cpu_elf_name, "v5"
0468
0469     .type   cpu_arm1020_name, #object
0470 cpu_arm1020_name:
0471     .ascii  "ARM1020"
0472 #ifndef CONFIG_CPU_ICACHE_DISABLE
0473     .ascii  "i"
0474 #endif
0475 #ifndef CONFIG_CPU_DCACHE_DISABLE
0476     .ascii  "d"
0477 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
0478     .ascii  "(wt)"
0479 #else
0480     .ascii  "(wb)"
0481 #endif
0482 #endif
0483 #ifndef CONFIG_CPU_BPREDICT_DISABLE
0484     .ascii  "B"
0485 #endif
0486 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
0487     .ascii  "RR"
0488 #endif
0489     .ascii  "\0"
0490     .size   cpu_arm1020_name, . - cpu_arm1020_name
0491
0492     .align
0493
0494     .section ".proc.info.init", "a"
0495
0496     .type   __arm1020_proc_info,#object
0497 __arm1020_proc_info:
0498     .long   0x4104a200          @ ARM 1020T (Architecture v5T)
0499     .long   0xff0ffff0
0500     .long   PMD_TYPE_SECT | \
0501         PMD_SECT_AP_WRITE | \
0502         PMD_SECT_AP_READ
0503     .long   PMD_TYPE_SECT | \
0504         PMD_SECT_AP_WRITE | \
0505         PMD_SECT_AP_READ
0506     initfn  __arm1020_setup, __arm1020_proc_info
0507     .long   cpu_arch_name
0508     .long   cpu_elf_name
0509     .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
0510     .long   cpu_arm1020_name
0511     .long   arm1020_processor_functions
0512     .long   v4wbi_tlb_fns
0513     .long   v4wb_user_fns
0514     .long   arm1020_cache_fns
0515     .size   __arm1020_proc_info, . - __arm1020_proc_info