arm/mm/nommu.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/mm/nommu.c
0004  *
0005  * ARM uCLinux supporting functions.
0006  */
0007 #include <linux/module.h>
0008 #include <linux/mm.h>
0009 #include <linux/pagemap.h>
0010 #include <linux/io.h>
0011 #include <linux/memblock.h>
0012 #include <linux/kernel.h>
0013
0014 #include <asm/cacheflush.h>
0015 #include <asm/cp15.h>
0016 #include <asm/sections.h>
0017 #include <asm/page.h>
0018 #include <asm/setup.h>
0019 #include <asm/traps.h>
0020 #include <asm/mach/arch.h>
0021 #include <asm/cputype.h>
0022 #include <asm/mpu.h>
0023 #include <asm/procinfo.h>
0024
0025 #include "mm.h"
0026
0027 unsigned long vectors_base;
0028
0029 #ifdef CONFIG_ARM_MPU
0030 struct mpu_rgn_info mpu_rgn_info;
0031 #endif
0032
0033 #ifdef CONFIG_CPU_CP15
0034 #ifdef CONFIG_CPU_HIGH_VECTOR
0035 unsigned long setup_vectors_base(void)
0036 {
0037     unsigned long reg = get_cr();
0038
0039     set_cr(reg | CR_V);
0040     return 0xffff0000;
0041 }
0042 #else /* CONFIG_CPU_HIGH_VECTOR */
0043 /* Write exception base address to VBAR */
0044 static inline void set_vbar(unsigned long val)
0045 {
0046     asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc");
0047 }
0048
0049 /*
0050  * Security extensions, bits[7:4], permitted values,
0051  * 0b0000 - not implemented, 0b0001/0b0010 - implemented
0052  */
0053 static inline bool security_extensions_enabled(void)
0054 {
0055     /* Check CPUID Identification Scheme before ID_PFR1 read */
0056     if ((read_cpuid_id() & 0x000f0000) == 0x000f0000)
0057         return cpuid_feature_extract(CPUID_EXT_PFR1, 4) ||
0058             cpuid_feature_extract(CPUID_EXT_PFR1, 20);
0059     return 0;
0060 }
0061
0062 unsigned long setup_vectors_base(void)
0063 {
0064     unsigned long base = 0, reg = get_cr();
0065
0066     set_cr(reg & ~CR_V);
0067     if (security_extensions_enabled()) {
0068         if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM))
0069             base = CONFIG_DRAM_BASE;
0070         set_vbar(base);
0071     } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) {
0072         if (CONFIG_DRAM_BASE != 0)
0073             pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n");
0074     }
0075
0076     return base;
0077 }
0078 #endif /* CONFIG_CPU_HIGH_VECTOR */
0079 #endif /* CONFIG_CPU_CP15 */
0080
0081 void __init arm_mm_memblock_reserve(void)
0082 {
0083 #ifndef CONFIG_CPU_V7M
0084     vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0;
0085     /*
0086      * Register the exception vector page.
0087      * some architectures which the DRAM is the exception vector to trap,
0088      * alloc_page breaks with error, although it is not NULL, but "0."
0089      */
0090     memblock_reserve(vectors_base, 2 * PAGE_SIZE);
0091 #else /* ifndef CONFIG_CPU_V7M */
0092     /*
0093      * There is no dedicated vector page on V7-M. So nothing needs to be
0094      * reserved here.
0095      */
0096 #endif
0097     /*
0098      * In any case, always ensure address 0 is never used as many things
0099      * get very confused if 0 is returned as a legitimate address.
0100      */
0101     memblock_reserve(0, 1);
0102 }
0103
0104 static void __init adjust_lowmem_bounds_mpu(void)
0105 {
0106     unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA;
0107
0108     switch (pmsa) {
0109     case MMFR0_PMSAv7:
0110         pmsav7_adjust_lowmem_bounds();
0111         break;
0112     case MMFR0_PMSAv8:
0113         pmsav8_adjust_lowmem_bounds();
0114         break;
0115     default:
0116         break;
0117     }
0118 }
0119
0120 static void __init mpu_setup(void)
0121 {
0122     unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA;
0123
0124     switch (pmsa) {
0125     case MMFR0_PMSAv7:
0126         pmsav7_setup();
0127         break;
0128     case MMFR0_PMSAv8:
0129         pmsav8_setup();
0130         break;
0131     default:
0132         break;
0133     }
0134 }
0135
0136 void __init adjust_lowmem_bounds(void)
0137 {
0138     phys_addr_t end;
0139     adjust_lowmem_bounds_mpu();
0140     end = memblock_end_of_DRAM();
0141     high_memory = __va(end - 1) + 1;
0142     memblock_set_current_limit(end);
0143 }
0144
0145 /*
0146  * paging_init() sets up the page tables, initialises the zone memory
0147  * maps, and sets up the zero page, bad page and bad page tables.
0148  */
0149 void __init paging_init(const struct machine_desc *mdesc)
0150 {
0151     early_trap_init((void *)vectors_base);
0152     mpu_setup();
0153     bootmem_init();
0154 }
0155
0156 /*
0157  * We don't need to do anything here for nommu machines.
0158  */
0159 void setup_mm_for_reboot(void)
0160 {
0161 }
0162
0163 void flush_dcache_page(struct page *page)
0164 {
0165     __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
0166 }
0167 EXPORT_SYMBOL(flush_dcache_page);
0168
0169 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
0170                unsigned long uaddr, void *dst, const void *src,
0171                unsigned long len)
0172 {
0173     memcpy(dst, src, len);
0174     if (vma->vm_flags & VM_EXEC)
0175         __cpuc_coherent_user_range(uaddr, uaddr + len);
0176 }
0177
0178 void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
0179                 size_t size, unsigned int mtype)
0180 {
0181     if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
0182         return NULL;
0183     return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
0184 }
0185 EXPORT_SYMBOL(__arm_ioremap_pfn);
0186
0187 void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
0188                    unsigned int mtype, void *caller)
0189 {
0190     return (void __iomem *)phys_addr;
0191 }
0192
0193 void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
0194
0195 void __iomem *ioremap(resource_size_t res_cookie, size_t size)
0196 {
0197     return __arm_ioremap_caller(res_cookie, size, MT_DEVICE,
0198                     __builtin_return_address(0));
0199 }
0200 EXPORT_SYMBOL(ioremap);
0201
0202 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
0203 {
0204     return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
0205                     __builtin_return_address(0));
0206 }
0207 EXPORT_SYMBOL(ioremap_cache);
0208
0209 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
0210 {
0211     return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC,
0212                     __builtin_return_address(0));
0213 }
0214 EXPORT_SYMBOL(ioremap_wc);
0215
0216 #ifdef CONFIG_PCI
0217
0218 #include <asm/mach/map.h>
0219
0220 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)
0221 {
0222     return arch_ioremap_caller(res_cookie, size, MT_UNCACHED,
0223                    __builtin_return_address(0));
0224 }
0225 EXPORT_SYMBOL_GPL(pci_remap_cfgspace);
0226 #endif
0227
0228 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size)
0229 {
0230     return (void *)phys_addr;
0231 }
0232
0233 void iounmap(volatile void __iomem *io_addr)
0234 {
0235 }
0236 EXPORT_SYMBOL(iounmap);