arm/mm/l2c-l2x0-resume.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * L2C-310 early resume code.  This can be used by platforms to restore
0004  * the settings of their L2 cache controller before restoring the
0005  * processor state.
0006  *
0007  * This code can only be used to if you are running in the secure world.
0008  */
0009 #include <linux/linkage.h>
0010 #include <asm/assembler.h>
0011 #include <asm/hardware/cache-l2x0.h>
0012
0013     .text
0014
0015 ENTRY(l2c310_early_resume)
0016     adr r0, 1f
0017     ldr r2, [r0]
0018     add r0, r2, r0
0019
0020     ldmia   r0, {r1, r2, r3, r4, r5, r6, r7, r8}
0021     @ r1 = phys address of L2C-310 controller
0022     @ r2 = aux_ctrl
0023     @ r3 = tag_latency
0024     @ r4 = data_latency
0025     @ r5 = filter_start
0026     @ r6 = filter_end
0027     @ r7 = prefetch_ctrl
0028     @ r8 = pwr_ctrl
0029
0030     @ Check that the address has been initialised
0031     teq r1, #0
0032     reteq   lr
0033
0034     @ The prefetch and power control registers are revision dependent
0035     @ and can be written whether or not the L2 cache is enabled
0036     ldr r0, [r1, #L2X0_CACHE_ID]
0037     and r0, r0, #L2X0_CACHE_ID_RTL_MASK
0038     cmp r0, #L310_CACHE_ID_RTL_R2P0
0039     strcs   r7, [r1, #L310_PREFETCH_CTRL]
0040     cmp r0, #L310_CACHE_ID_RTL_R3P0
0041     strcs   r8, [r1, #L310_POWER_CTRL]
0042
0043     @ Don't setup the L2 cache if it is already enabled
0044     ldr r0, [r1, #L2X0_CTRL]
0045     tst r0, #L2X0_CTRL_EN
0046     retne   lr
0047
0048     str r3, [r1, #L310_TAG_LATENCY_CTRL]
0049     str r4, [r1, #L310_DATA_LATENCY_CTRL]
0050     str r6, [r1, #L310_ADDR_FILTER_END]
0051     str r5, [r1, #L310_ADDR_FILTER_START]
0052
0053     str r2, [r1, #L2X0_AUX_CTRL]
0054     mov r9, #L2X0_CTRL_EN
0055     str r9, [r1, #L2X0_CTRL]
0056     ret lr
0057 ENDPROC(l2c310_early_resume)
0058
0059     .align
0060 1:  .long   l2x0_saved_regs - .