arm/mm/dma-mapping-nommu.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Based on linux/arch/arm/mm/dma-mapping.c
0004  *
0005  *  Copyright (C) 2000-2004 Russell King
0006  */
0007
0008 #include <linux/dma-map-ops.h>
0009 #include <asm/cachetype.h>
0010 #include <asm/cacheflush.h>
0011 #include <asm/outercache.h>
0012 #include <asm/cp15.h>
0013
0014 #include "dma.h"
0015
0016 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
0017         enum dma_data_direction dir)
0018 {
0019     dmac_map_area(__va(paddr), size, dir);
0020
0021     if (dir == DMA_FROM_DEVICE)
0022         outer_inv_range(paddr, paddr + size);
0023     else
0024         outer_clean_range(paddr, paddr + size);
0025 }
0026
0027 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
0028         enum dma_data_direction dir)
0029 {
0030     if (dir != DMA_TO_DEVICE) {
0031         outer_inv_range(paddr, paddr + size);
0032         dmac_unmap_area(__va(paddr), size, dir);
0033     }
0034 }
0035
0036 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
0037             const struct iommu_ops *iommu, bool coherent)
0038 {
0039     if (IS_ENABLED(CONFIG_CPU_V7M)) {
0040         /*
0041          * Cache support for v7m is optional, so can be treated as
0042          * coherent if no cache has been detected. Note that it is not
0043          * enough to check if MPU is in use or not since in absense of
0044          * MPU system memory map is used.
0045          */
0046         dev->dma_coherent = cacheid ? coherent : true;
0047     } else {
0048         /*
0049          * Assume coherent DMA in case MMU/MPU has not been set up.
0050          */
0051         dev->dma_coherent = (get_cr() & CR_M) ? coherent : true;
0052     }
0053 }