arm/mm/copypage-v4mc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/lib/copypage-armv4mc.S
0004  *
0005  *  Copyright (C) 1995-2005 Russell King
0006  *
0007  * This handles the mini data cache, as found on SA11x0 and XScale
0008  * processors.  When we copy a user page page, we map it in such a way
0009  * that accesses to this page will not touch the main data cache, but
0010  * will be cached in the mini data cache.  This prevents us thrashing
0011  * the main data cache on page faults.
0012  */
0013 #include <linux/init.h>
0014 #include <linux/mm.h>
0015 #include <linux/highmem.h>
0016 #include <linux/pagemap.h>
0017
0018 #include <asm/tlbflush.h>
0019 #include <asm/cacheflush.h>
0020
0021 #include "mm.h"
0022
0023 #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
0024                   L_PTE_MT_MINICACHE)
0025
0026 static DEFINE_RAW_SPINLOCK(minicache_lock);
0027
0028 /*
0029  * ARMv4 mini-dcache optimised copy_user_highpage
0030  *
0031  * We flush the destination cache lines just before we write the data into the
0032  * corresponding address.  Since the Dcache is read-allocate, this removes the
0033  * Dcache aliasing issue.  The writes will be forwarded to the write buffer,
0034  * and merged as appropriate.
0035  *
0036  * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
0037  * instruction.  If your processor does not supply this, you have to write your
0038  * own copy_user_highpage that does the right thing.
0039  */
0040 static void mc_copy_user_page(void *from, void *to)
0041 {
0042     int tmp;
0043
0044     asm volatile ("\
0045     .syntax unified\n\
0046     ldmia   %0!, {r2, r3, ip, lr}       @ 4\n\
0047 1:  mcr p15, 0, %1, c7, c6, 1       @ 1   invalidate D line\n\
0048     stmia   %1!, {r2, r3, ip, lr}       @ 4\n\
0049     ldmia   %0!, {r2, r3, ip, lr}       @ 4+1\n\
0050     stmia   %1!, {r2, r3, ip, lr}       @ 4\n\
0051     ldmia   %0!, {r2, r3, ip, lr}       @ 4\n\
0052     mcr p15, 0, %1, c7, c6, 1       @ 1   invalidate D line\n\
0053     stmia   %1!, {r2, r3, ip, lr}       @ 4\n\
0054     ldmia   %0!, {r2, r3, ip, lr}       @ 4\n\
0055     subs    %2, %2, #1          @ 1\n\
0056     stmia   %1!, {r2, r3, ip, lr}       @ 4\n\
0057     ldmiane %0!, {r2, r3, ip, lr}       @ 4\n\
0058     bne 1b              @ "
0059     : "+&r" (from), "+&r" (to), "=&r" (tmp)
0060     : "2" (PAGE_SIZE / 64)
0061     : "r2", "r3", "ip", "lr");
0062 }
0063
0064 void v4_mc_copy_user_highpage(struct page *to, struct page *from,
0065     unsigned long vaddr, struct vm_area_struct *vma)
0066 {
0067     void *kto = kmap_atomic(to);
0068
0069     if (!test_and_set_bit(PG_dcache_clean, &from->flags))
0070         __flush_dcache_page(page_mapping_file(from), from);
0071
0072     raw_spin_lock(&minicache_lock);
0073
0074     set_top_pte(COPYPAGE_MINICACHE, mk_pte(from, minicache_pgprot));
0075
0076     mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
0077
0078     raw_spin_unlock(&minicache_lock);
0079
0080     kunmap_atomic(kto);
0081 }
0082
0083 /*
0084  * ARMv4 optimised clear_user_page
0085  */
0086 void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
0087 {
0088     void *ptr, *kaddr = kmap_atomic(page);
0089     asm volatile("\
0090     mov r1, %2              @ 1\n\
0091     mov r2, #0              @ 1\n\
0092     mov r3, #0              @ 1\n\
0093     mov ip, #0              @ 1\n\
0094     mov lr, #0              @ 1\n\
0095 1:  mcr p15, 0, %0, c7, c6, 1       @ 1   invalidate D line\n\
0096     stmia   %0!, {r2, r3, ip, lr}       @ 4\n\
0097     stmia   %0!, {r2, r3, ip, lr}       @ 4\n\
0098     mcr p15, 0, %0, c7, c6, 1       @ 1   invalidate D line\n\
0099     stmia   %0!, {r2, r3, ip, lr}       @ 4\n\
0100     stmia   %0!, {r2, r3, ip, lr}       @ 4\n\
0101     subs    r1, r1, #1          @ 1\n\
0102     bne 1b              @ 1"
0103     : "=r" (ptr)
0104     : "0" (kaddr), "I" (PAGE_SIZE / 64)
0105     : "r1", "r2", "r3", "ip", "lr");
0106     kunmap_atomic(kaddr);
0107 }
0108
0109 struct cpu_user_fns v4_mc_user_fns __initdata = {
0110     .cpu_clear_user_highpage = v4_mc_clear_user_highpage,
0111     .cpu_copy_user_highpage = v4_mc_copy_user_highpage,
0112 };