arm/mm/cache-tauros3.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Marvell Tauros3 cache controller includes
0004  *
0005  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0006  *
0007  * based on GPL'ed 2.6 kernel sources
0008  *  (c) Marvell International Ltd.
0009  */
0010
0011 #ifndef __ASM_ARM_HARDWARE_TAUROS3_H
0012 #define __ASM_ARM_HARDWARE_TAUROS3_H
0013
0014 /*
0015  * Marvell Tauros3 L2CC is compatible with PL310 r0p0
0016  * but with PREFETCH_CTRL (r2p0) and an additional event counter.
0017  * Also, there is AUX2_CTRL for some Marvell specific control.
0018  */
0019
0020 #define TAUROS3_EVENT_CNT2_CFG      0x224
0021 #define TAUROS3_EVENT_CNT2_VAL      0x228
0022 #define TAUROS3_INV_ALL         0x780
0023 #define TAUROS3_CLEAN_ALL       0x784
0024 #define TAUROS3_AUX2_CTRL       0x820
0025
0026 /* Registers shifts and masks */
0027 #define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN    (1 << 2)
0028
0029 #endif