arm/mm/cache-tauros2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
0004  *
0005  * Copyright (C) 2008 Marvell Semiconductor
0006  *
0007  * References:
0008  * - PJ1 CPU Core Datasheet,
0009  *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
0010  * - PJ4 CPU Core Datasheet,
0011  *   Document ID MV-S105190-00, Rev 0.7, March 14 2008.
0012  */
0013
0014 #include <linux/init.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <asm/cacheflush.h>
0018 #include <asm/cp15.h>
0019 #include <asm/cputype.h>
0020 #include <asm/hardware/cache-tauros2.h>
0021
0022 /* CP15 PJ4 Control configuration register */
0023 #define CCR_L2C_PREFETCH_DISABLE    BIT(24)
0024 #define CCR_L2C_ECC_ENABLE      BIT(23)
0025 #define CCR_L2C_WAY7_4_DISABLE      BIT(21)
0026 #define CCR_L2C_BURST8_ENABLE       BIT(20)
0027
0028 /*
0029  * When Tauros2 is used on a CPU that supports the v7 hierarchical
0030  * cache operations, the cache handling code in proc-v7.S takes care
0031  * of everything, including handling DMA coherency.
0032  *
0033  * So, we only need to register outer cache operations here if we're
0034  * being used on a pre-v7 CPU, and we only need to build support for
0035  * outer cache operations into the kernel image if the kernel has been
0036  * configured to support a pre-v7 CPU.
0037  */
0038 #ifdef CONFIG_CPU_32v5
0039 /*
0040  * Low-level cache maintenance operations.
0041  */
0042 static inline void tauros2_clean_pa(unsigned long addr)
0043 {
0044     __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
0045 }
0046
0047 static inline void tauros2_clean_inv_pa(unsigned long addr)
0048 {
0049     __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
0050 }
0051
0052 static inline void tauros2_inv_pa(unsigned long addr)
0053 {
0054     __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
0055 }
0056
0057
0058 /*
0059  * Linux primitives.
0060  *
0061  * Note that the end addresses passed to Linux primitives are
0062  * noninclusive.
0063  */
0064 #define CACHE_LINE_SIZE     32
0065
0066 static void tauros2_inv_range(unsigned long start, unsigned long end)
0067 {
0068     /*
0069      * Clean and invalidate partial first cache line.
0070      */
0071     if (start & (CACHE_LINE_SIZE - 1)) {
0072         tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
0073         start = (start | (CACHE_LINE_SIZE - 1)) + 1;
0074     }
0075
0076     /*
0077      * Clean and invalidate partial last cache line.
0078      */
0079     if (end & (CACHE_LINE_SIZE - 1)) {
0080         tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
0081         end &= ~(CACHE_LINE_SIZE - 1);
0082     }
0083
0084     /*
0085      * Invalidate all full cache lines between 'start' and 'end'.
0086      */
0087     while (start < end) {
0088         tauros2_inv_pa(start);
0089         start += CACHE_LINE_SIZE;
0090     }
0091
0092     dsb();
0093 }
0094
0095 static void tauros2_clean_range(unsigned long start, unsigned long end)
0096 {
0097     start &= ~(CACHE_LINE_SIZE - 1);
0098     while (start < end) {
0099         tauros2_clean_pa(start);
0100         start += CACHE_LINE_SIZE;
0101     }
0102
0103     dsb();
0104 }
0105
0106 static void tauros2_flush_range(unsigned long start, unsigned long end)
0107 {
0108     start &= ~(CACHE_LINE_SIZE - 1);
0109     while (start < end) {
0110         tauros2_clean_inv_pa(start);
0111         start += CACHE_LINE_SIZE;
0112     }
0113
0114     dsb();
0115 }
0116
0117 static void tauros2_disable(void)
0118 {
0119     __asm__ __volatile__ (
0120     "mcr    p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t"
0121     "mrc    p15, 0, %0, c1, c0, 0\n\t"
0122     "bic    %0, %0, #(1 << 26)\n\t"
0123     "mcr    p15, 0, %0, c1, c0, 0  @Disable L2 Cache\n\t"
0124     : : "r" (0x0));
0125 }
0126
0127 static void tauros2_resume(void)
0128 {
0129     __asm__ __volatile__ (
0130     "mcr    p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t"
0131     "mrc    p15, 0, %0, c1, c0, 0\n\t"
0132     "orr    %0, %0, #(1 << 26)\n\t"
0133     "mcr    p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t"
0134     : : "r" (0x0));
0135 }
0136 #endif
0137
0138 static inline u32 __init read_extra_features(void)
0139 {
0140     u32 u;
0141
0142     __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
0143
0144     return u;
0145 }
0146
0147 static inline void __init write_extra_features(u32 u)
0148 {
0149     __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
0150 }
0151
0152 static inline int __init cpuid_scheme(void)
0153 {
0154     return !!((processor_id & 0x000f0000) == 0x000f0000);
0155 }
0156
0157 static inline u32 __init read_mmfr3(void)
0158 {
0159     u32 mmfr3;
0160
0161     __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));
0162
0163     return mmfr3;
0164 }
0165
0166 static inline u32 __init read_actlr(void)
0167 {
0168     u32 actlr;
0169
0170     __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
0171
0172     return actlr;
0173 }
0174
0175 static inline void __init write_actlr(u32 actlr)
0176 {
0177     __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
0178 }
0179
0180 static void enable_extra_feature(unsigned int features)
0181 {
0182     u32 u;
0183
0184     u = read_extra_features();
0185
0186     if (features & CACHE_TAUROS2_PREFETCH_ON)
0187         u &= ~CCR_L2C_PREFETCH_DISABLE;
0188     else
0189         u |= CCR_L2C_PREFETCH_DISABLE;
0190     pr_info("Tauros2: %s L2 prefetch.\n",
0191             (features & CACHE_TAUROS2_PREFETCH_ON)
0192             ? "Enabling" : "Disabling");
0193
0194     if (features & CACHE_TAUROS2_LINEFILL_BURST8)
0195         u |= CCR_L2C_BURST8_ENABLE;
0196     else
0197         u &= ~CCR_L2C_BURST8_ENABLE;
0198     pr_info("Tauros2: %s burst8 line fill.\n",
0199             (features & CACHE_TAUROS2_LINEFILL_BURST8)
0200             ? "Enabling" : "Disabling");
0201
0202     write_extra_features(u);
0203 }
0204
0205 static void __init tauros2_internal_init(unsigned int features)
0206 {
0207     char *mode = NULL;
0208
0209     enable_extra_feature(features);
0210
0211 #ifdef CONFIG_CPU_32v5
0212     if ((processor_id & 0xff0f0000) == 0x56050000) {
0213         u32 feat;
0214
0215         /*
0216          * v5 CPUs with Tauros2 have the L2 cache enable bit
0217          * located in the CPU Extra Features register.
0218          */
0219         feat = read_extra_features();
0220         if (!(feat & 0x00400000)) {
0221             pr_info("Tauros2: Enabling L2 cache.\n");
0222             write_extra_features(feat | 0x00400000);
0223         }
0224
0225         mode = "ARMv5";
0226         outer_cache.inv_range = tauros2_inv_range;
0227         outer_cache.clean_range = tauros2_clean_range;
0228         outer_cache.flush_range = tauros2_flush_range;
0229         outer_cache.disable = tauros2_disable;
0230         outer_cache.resume = tauros2_resume;
0231     }
0232 #endif
0233
0234 #ifdef CONFIG_CPU_32v7
0235     /*
0236      * Check whether this CPU has support for the v7 hierarchical
0237      * cache ops.  (PJ4 is in its v7 personality mode if the MMFR3
0238      * register indicates support for the v7 hierarchical cache
0239      * ops.)
0240      *
0241      * (Although strictly speaking there may exist CPUs that
0242      * implement the v7 cache ops but are only ARMv6 CPUs (due to
0243      * not complying with all of the other ARMv7 requirements),
0244      * there are no real-life examples of Tauros2 being used on
0245      * such CPUs as of yet.)
0246      */
0247     if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
0248         u32 actlr;
0249
0250         /*
0251          * When Tauros2 is used in an ARMv7 system, the L2
0252          * enable bit is located in the Auxiliary System Control
0253          * Register (which is the only register allowed by the
0254          * ARMv7 spec to contain fine-grained cache control bits).
0255          */
0256         actlr = read_actlr();
0257         if (!(actlr & 0x00000002)) {
0258             pr_info("Tauros2: Enabling L2 cache.\n");
0259             write_actlr(actlr | 0x00000002);
0260         }
0261
0262         mode = "ARMv7";
0263     }
0264 #endif
0265
0266     if (mode == NULL) {
0267         pr_crit("Tauros2: Unable to detect CPU mode.\n");
0268         return;
0269     }
0270
0271     pr_info("Tauros2: L2 cache support initialised "
0272              "in %s mode.\n", mode);
0273 }
0274
0275 #ifdef CONFIG_OF
0276 static const struct of_device_id tauros2_ids[] __initconst = {
0277     { .compatible = "marvell,tauros2-cache"},
0278     {}
0279 };
0280 #endif
0281
0282 void __init tauros2_init(unsigned int features)
0283 {
0284 #ifdef CONFIG_OF
0285     struct device_node *node;
0286     int ret;
0287     unsigned int f;
0288
0289     node = of_find_matching_node(NULL, tauros2_ids);
0290     if (!node) {
0291         pr_info("Not found marvell,tauros2-cache, disable it\n");
0292     } else {
0293         ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f);
0294         if (ret) {
0295             pr_info("Not found marvell,tauros-cache-features property, "
0296                 "disable extra features\n");
0297             features = 0;
0298         } else
0299             features = f;
0300     }
0301 #endif
0302     tauros2_internal_init(features);
0303 }