arm/mm/abort-macro.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
0004  * differently than every other instruction, so it is set to 0 (write)
0005  * even though the instructions are read instructions. This means that
0006  * during an abort the instructions will be treated as a write and the
0007  * handler will raise a signal from unwriteable locations if they
0008  * fault. We have to specifically check for these instructions
0009  * from the abort handlers to treat them properly.
0010  *
0011  */
0012
0013     .macro  do_thumb_abort, fsr, pc, psr, tmp
0014     tst \psr, #PSR_T_BIT
0015     beq not_thumb
0016     ldrh    \tmp, [\pc]         @ Read aborted Thumb instruction
0017     uaccess_disable ip          @ disable userspace access
0018     and \tmp, \tmp, # 0xfe00        @ Mask opcode field
0019     cmp \tmp, # 0x5600          @ Is it ldrsb?
0020     orreq   \tmp, \tmp, #1 << 11        @ Set L-bit if yes
0021     tst \tmp, #1 << 11          @ L = 0 -> write
0022     orreq   \fsr, \fsr, #1 << 11        @ yes.
0023     b   do_DataAbort
0024 not_thumb:
0025     .endm
0026
0027 /*
0028  * We check for the following instruction encoding for LDRD.
0029  *
0030  * [27:25] == 000
0031  *   [7:4] == 1101
0032  *    [20] == 0
0033  */
0034     .macro  teq_ldrd, tmp, insn
0035     mov \tmp, #0x0e100000
0036     orr \tmp, #0x000000f0
0037     and \tmp, \insn, \tmp
0038     teq \tmp, #0x000000d0
0039     .endm