0001 # SPDX-License-Identifier: GPL-2.0
0002 comment "Processor Type"
0003
0004 # Select CPU types depending on the architecture selected. This selects
0005 # which CPUs we support in the kernel image, and the compiler instruction
0006 # optimiser behaviour.
0007
0008 # ARM7TDMI
0009 config CPU_ARM7TDMI
0010 bool
0011 depends on !MMU
0012 select CPU_32v4T
0013 select CPU_ABRT_LV4T
0014 select CPU_CACHE_V4
0015 select CPU_PABRT_LEGACY
0016 help
0017 A 32-bit RISC microprocessor based on the ARM7 processor core
0018 which has no memory control unit and cache.
0019
0020 Say Y if you want support for the ARM7TDMI processor.
0021 Otherwise, say N.
0022
0023 # ARM720T
0024 config CPU_ARM720T
0025 bool
0026 select CPU_32v4T
0027 select CPU_ABRT_LV4T
0028 select CPU_CACHE_V4
0029 select CPU_CACHE_VIVT
0030 select CPU_COPY_V4WT if MMU
0031 select CPU_CP15_MMU
0032 select CPU_PABRT_LEGACY
0033 select CPU_THUMB_CAPABLE
0034 select CPU_TLB_V4WT if MMU
0035 help
0036 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
0037 MMU built around an ARM7TDMI core.
0038
0039 Say Y if you want support for the ARM720T processor.
0040 Otherwise, say N.
0041
0042 # ARM740T
0043 config CPU_ARM740T
0044 bool
0045 depends on !MMU
0046 select CPU_32v4T
0047 select CPU_ABRT_LV4T
0048 select CPU_CACHE_V4
0049 select CPU_CP15_MPU
0050 select CPU_PABRT_LEGACY
0051 select CPU_THUMB_CAPABLE
0052 help
0053 A 32-bit RISC processor with 8KB cache or 4KB variants,
0054 write buffer and MPU(Protection Unit) built around
0055 an ARM7TDMI core.
0056
0057 Say Y if you want support for the ARM740T processor.
0058 Otherwise, say N.
0059
0060 # ARM9TDMI
0061 config CPU_ARM9TDMI
0062 bool
0063 depends on !MMU
0064 select CPU_32v4T
0065 select CPU_ABRT_NOMMU
0066 select CPU_CACHE_V4
0067 select CPU_PABRT_LEGACY
0068 help
0069 A 32-bit RISC microprocessor based on the ARM9 processor core
0070 which has no memory control unit and cache.
0071
0072 Say Y if you want support for the ARM9TDMI processor.
0073 Otherwise, say N.
0074
0075 # ARM920T
0076 config CPU_ARM920T
0077 bool
0078 select CPU_32v4T
0079 select CPU_ABRT_EV4T
0080 select CPU_CACHE_V4WT
0081 select CPU_CACHE_VIVT
0082 select CPU_COPY_V4WB if MMU
0083 select CPU_CP15_MMU
0084 select CPU_PABRT_LEGACY
0085 select CPU_THUMB_CAPABLE
0086 select CPU_TLB_V4WBI if MMU
0087 help
0088 The ARM920T is licensed to be produced by numerous vendors,
0089 and is used in the Cirrus EP93xx and the Samsung S3C2410.
0090
0091 Say Y if you want support for the ARM920T processor.
0092 Otherwise, say N.
0093
0094 # ARM922T
0095 config CPU_ARM922T
0096 bool
0097 select CPU_32v4T
0098 select CPU_ABRT_EV4T
0099 select CPU_CACHE_V4WT
0100 select CPU_CACHE_VIVT
0101 select CPU_COPY_V4WB if MMU
0102 select CPU_CP15_MMU
0103 select CPU_PABRT_LEGACY
0104 select CPU_THUMB_CAPABLE
0105 select CPU_TLB_V4WBI if MMU
0106 help
0107 The ARM922T is a version of the ARM920T, but with smaller
0108 instruction and data caches. It is used in Altera's
0109 Excalibur XA device family and the ARM Integrator.
0110
0111 Say Y if you want support for the ARM922T processor.
0112 Otherwise, say N.
0113
0114 # ARM925T
0115 config CPU_ARM925T
0116 bool
0117 select CPU_32v4T
0118 select CPU_ABRT_EV4T
0119 select CPU_CACHE_V4WT
0120 select CPU_CACHE_VIVT
0121 select CPU_COPY_V4WB if MMU
0122 select CPU_CP15_MMU
0123 select CPU_PABRT_LEGACY
0124 select CPU_THUMB_CAPABLE
0125 select CPU_TLB_V4WBI if MMU
0126 help
0127 The ARM925T is a mix between the ARM920T and ARM926T, but with
0128 different instruction and data caches. It is used in TI's OMAP
0129 device family.
0130
0131 Say Y if you want support for the ARM925T processor.
0132 Otherwise, say N.
0133
0134 # ARM926T
0135 config CPU_ARM926T
0136 bool
0137 select CPU_32v5
0138 select CPU_ABRT_EV5TJ
0139 select CPU_CACHE_VIVT
0140 select CPU_COPY_V4WB if MMU
0141 select CPU_CP15_MMU
0142 select CPU_PABRT_LEGACY
0143 select CPU_THUMB_CAPABLE
0144 select CPU_TLB_V4WBI if MMU
0145 help
0146 This is a variant of the ARM920. It has slightly different
0147 instruction sequences for cache and TLB operations. Curiously,
0148 there is no documentation on it at the ARM corporate website.
0149
0150 Say Y if you want support for the ARM926T processor.
0151 Otherwise, say N.
0152
0153 # FA526
0154 config CPU_FA526
0155 bool
0156 select CPU_32v4
0157 select CPU_ABRT_EV4
0158 select CPU_CACHE_FA
0159 select CPU_CACHE_VIVT
0160 select CPU_COPY_FA if MMU
0161 select CPU_CP15_MMU
0162 select CPU_PABRT_LEGACY
0163 select CPU_TLB_FA if MMU
0164 help
0165 The FA526 is a version of the ARMv4 compatible processor with
0166 Branch Target Buffer, Unified TLB and cache line size 16.
0167
0168 Say Y if you want support for the FA526 processor.
0169 Otherwise, say N.
0170
0171 # ARM940T
0172 config CPU_ARM940T
0173 bool
0174 depends on !MMU
0175 select CPU_32v4T
0176 select CPU_ABRT_NOMMU
0177 select CPU_CACHE_VIVT
0178 select CPU_CP15_MPU
0179 select CPU_PABRT_LEGACY
0180 select CPU_THUMB_CAPABLE
0181 help
0182 ARM940T is a member of the ARM9TDMI family of general-
0183 purpose microprocessors with MPU and separate 4KB
0184 instruction and 4KB data cases, each with a 4-word line
0185 length.
0186
0187 Say Y if you want support for the ARM940T processor.
0188 Otherwise, say N.
0189
0190 # ARM946E-S
0191 config CPU_ARM946E
0192 bool
0193 depends on !MMU
0194 select CPU_32v5
0195 select CPU_ABRT_NOMMU
0196 select CPU_CACHE_VIVT
0197 select CPU_CP15_MPU
0198 select CPU_PABRT_LEGACY
0199 select CPU_THUMB_CAPABLE
0200 help
0201 ARM946E-S is a member of the ARM9E-S family of high-
0202 performance, 32-bit system-on-chip processor solutions.
0203 The TCM and ARMv5TE 32-bit instruction set is supported.
0204
0205 Say Y if you want support for the ARM946E-S processor.
0206 Otherwise, say N.
0207
0208 # ARM1020 - needs validating
0209 config CPU_ARM1020
0210 bool
0211 select CPU_32v5
0212 select CPU_ABRT_EV4T
0213 select CPU_CACHE_V4WT
0214 select CPU_CACHE_VIVT
0215 select CPU_COPY_V4WB if MMU
0216 select CPU_CP15_MMU
0217 select CPU_PABRT_LEGACY
0218 select CPU_THUMB_CAPABLE
0219 select CPU_TLB_V4WBI if MMU
0220 help
0221 The ARM1020 is the 32K cached version of the ARM10 processor,
0222 with an addition of a floating-point unit.
0223
0224 Say Y if you want support for the ARM1020 processor.
0225 Otherwise, say N.
0226
0227 # ARM1020E - needs validating
0228 config CPU_ARM1020E
0229 bool
0230 depends on n
0231 select CPU_32v5
0232 select CPU_ABRT_EV4T
0233 select CPU_CACHE_V4WT
0234 select CPU_CACHE_VIVT
0235 select CPU_COPY_V4WB if MMU
0236 select CPU_CP15_MMU
0237 select CPU_PABRT_LEGACY
0238 select CPU_THUMB_CAPABLE
0239 select CPU_TLB_V4WBI if MMU
0240
0241 # ARM1022E
0242 config CPU_ARM1022
0243 bool
0244 select CPU_32v5
0245 select CPU_ABRT_EV4T
0246 select CPU_CACHE_VIVT
0247 select CPU_COPY_V4WB if MMU # can probably do better
0248 select CPU_CP15_MMU
0249 select CPU_PABRT_LEGACY
0250 select CPU_THUMB_CAPABLE
0251 select CPU_TLB_V4WBI if MMU
0252 help
0253 The ARM1022E is an implementation of the ARMv5TE architecture
0254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
0255 embedded trace macrocell, and a floating-point unit.
0256
0257 Say Y if you want support for the ARM1022E processor.
0258 Otherwise, say N.
0259
0260 # ARM1026EJ-S
0261 config CPU_ARM1026
0262 bool
0263 select CPU_32v5
0264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
0265 select CPU_CACHE_VIVT
0266 select CPU_COPY_V4WB if MMU # can probably do better
0267 select CPU_CP15_MMU
0268 select CPU_PABRT_LEGACY
0269 select CPU_THUMB_CAPABLE
0270 select CPU_TLB_V4WBI if MMU
0271 help
0272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
0273 based upon the ARM10 integer core.
0274
0275 Say Y if you want support for the ARM1026EJ-S processor.
0276 Otherwise, say N.
0277
0278 # SA110
0279 config CPU_SA110
0280 bool
0281 select CPU_32v3 if ARCH_RPC
0282 select CPU_32v4 if !ARCH_RPC
0283 select CPU_ABRT_EV4
0284 select CPU_CACHE_V4WB
0285 select CPU_CACHE_VIVT
0286 select CPU_COPY_V4WB if MMU
0287 select CPU_CP15_MMU
0288 select CPU_PABRT_LEGACY
0289 select CPU_TLB_V4WB if MMU
0290 help
0291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
0292 is available at five speeds ranging from 100 MHz to 233 MHz.
0293 More information is available at
0294 <http://developer.intel.com/design/strong/sa110.htm>.
0295
0296 Say Y if you want support for the SA-110 processor.
0297 Otherwise, say N.
0298
0299 # SA1100
0300 config CPU_SA1100
0301 bool
0302 select CPU_32v4
0303 select CPU_ABRT_EV4
0304 select CPU_CACHE_V4WB
0305 select CPU_CACHE_VIVT
0306 select CPU_CP15_MMU
0307 select CPU_PABRT_LEGACY
0308 select CPU_TLB_V4WB if MMU
0309
0310 # XScale
0311 config CPU_XSCALE
0312 bool
0313 select CPU_32v5
0314 select CPU_ABRT_EV5T
0315 select CPU_CACHE_VIVT
0316 select CPU_CP15_MMU
0317 select CPU_PABRT_LEGACY
0318 select CPU_THUMB_CAPABLE
0319 select CPU_TLB_V4WBI if MMU
0320
0321 # XScale Core Version 3
0322 config CPU_XSC3
0323 bool
0324 select CPU_32v5
0325 select CPU_ABRT_EV5T
0326 select CPU_CACHE_VIVT
0327 select CPU_CP15_MMU
0328 select CPU_PABRT_LEGACY
0329 select CPU_THUMB_CAPABLE
0330 select CPU_TLB_V4WBI if MMU
0331 select IO_36
0332
0333 # Marvell PJ1 (Mohawk)
0334 config CPU_MOHAWK
0335 bool
0336 select CPU_32v5
0337 select CPU_ABRT_EV5T
0338 select CPU_CACHE_VIVT
0339 select CPU_COPY_V4WB if MMU
0340 select CPU_CP15_MMU
0341 select CPU_PABRT_LEGACY
0342 select CPU_THUMB_CAPABLE
0343 select CPU_TLB_V4WBI if MMU
0344
0345 # Feroceon
0346 config CPU_FEROCEON
0347 bool
0348 select CPU_32v5
0349 select CPU_ABRT_EV5T
0350 select CPU_CACHE_VIVT
0351 select CPU_COPY_FEROCEON if MMU
0352 select CPU_CP15_MMU
0353 select CPU_PABRT_LEGACY
0354 select CPU_THUMB_CAPABLE
0355 select CPU_TLB_FEROCEON if MMU
0356
0357 config CPU_FEROCEON_OLD_ID
0358 bool "Accept early Feroceon cores with an ARM926 ID"
0359 depends on CPU_FEROCEON && !CPU_ARM926T
0360 default y
0361 help
0362 This enables the usage of some old Feroceon cores
0363 for which the CPU ID is equal to the ARM926 ID.
0364 Relevant for Feroceon-1850 and early Feroceon-2850.
0365
0366 # Marvell PJ4
0367 config CPU_PJ4
0368 bool
0369 select ARM_THUMBEE
0370 select CPU_V7
0371
0372 config CPU_PJ4B
0373 bool
0374 select CPU_V7
0375
0376 # ARMv6
0377 config CPU_V6
0378 bool
0379 select CPU_32v6
0380 select CPU_ABRT_EV6
0381 select CPU_CACHE_V6
0382 select CPU_CACHE_VIPT
0383 select CPU_COPY_V6 if MMU
0384 select CPU_CP15_MMU
0385 select CPU_HAS_ASID if MMU
0386 select CPU_PABRT_V6
0387 select CPU_THUMB_CAPABLE
0388 select CPU_TLB_V6 if MMU
0389 select SMP_ON_UP if SMP
0390
0391 # ARMv6k
0392 config CPU_V6K
0393 bool
0394 select CPU_32v6
0395 select CPU_32v6K
0396 select CPU_ABRT_EV6
0397 select CPU_CACHE_V6
0398 select CPU_CACHE_VIPT
0399 select CPU_COPY_V6 if MMU
0400 select CPU_CP15_MMU
0401 select CPU_HAS_ASID if MMU
0402 select CPU_PABRT_V6
0403 select CPU_THUMB_CAPABLE
0404 select CPU_TLB_V6 if MMU
0405
0406 # ARMv7
0407 config CPU_V7
0408 bool
0409 select CPU_32v6K
0410 select CPU_32v7
0411 select CPU_ABRT_EV7
0412 select CPU_CACHE_V7
0413 select CPU_CACHE_VIPT
0414 select CPU_COPY_V6 if MMU
0415 select CPU_CP15_MMU if MMU
0416 select CPU_CP15_MPU if !MMU
0417 select CPU_HAS_ASID if MMU
0418 select CPU_PABRT_V7
0419 select CPU_SPECTRE if MMU
0420 select CPU_THUMB_CAPABLE
0421 select CPU_TLB_V7 if MMU
0422
0423 # ARMv7M
0424 config CPU_V7M
0425 bool
0426 select CPU_32v7M
0427 select CPU_ABRT_NOMMU
0428 select CPU_CACHE_V7M
0429 select CPU_CACHE_NOP
0430 select CPU_PABRT_LEGACY
0431 select CPU_THUMBONLY
0432
0433 config CPU_THUMBONLY
0434 bool
0435 select CPU_THUMB_CAPABLE
0436 # There are no CPUs available with MMU that don't implement an ARM ISA:
0437 depends on !MMU
0438 help
0439 Select this if your CPU doesn't support the 32 bit ARM instructions.
0440
0441 config CPU_THUMB_CAPABLE
0442 bool
0443 help
0444 Select this if your CPU can support Thumb mode.
0445
0446 # Figure out what processor architecture version we should be using.
0447 # This defines the compiler instruction set which depends on the machine type.
0448 config CPU_32v3
0449 bool
0450 select CPU_USE_DOMAINS if MMU
0451 select NEED_KUSER_HELPERS
0452 select TLS_REG_EMUL if SMP || !MMU
0453 select CPU_NO_EFFICIENT_FFS
0454
0455 config CPU_32v4
0456 bool
0457 select CPU_USE_DOMAINS if MMU
0458 select NEED_KUSER_HELPERS
0459 select TLS_REG_EMUL if SMP || !MMU
0460 select CPU_NO_EFFICIENT_FFS
0461
0462 config CPU_32v4T
0463 bool
0464 select CPU_USE_DOMAINS if MMU
0465 select NEED_KUSER_HELPERS
0466 select TLS_REG_EMUL if SMP || !MMU
0467 select CPU_NO_EFFICIENT_FFS
0468
0469 config CPU_32v5
0470 bool
0471 select CPU_USE_DOMAINS if MMU
0472 select NEED_KUSER_HELPERS
0473 select TLS_REG_EMUL if SMP || !MMU
0474
0475 config CPU_32v6
0476 bool
0477 select TLS_REG_EMUL if !CPU_32v6K && !MMU
0478
0479 config CPU_32v6K
0480 bool
0481
0482 config CPU_32v7
0483 bool
0484
0485 config CPU_32v7M
0486 bool
0487
0488 # The abort model
0489 config CPU_ABRT_NOMMU
0490 bool
0491
0492 config CPU_ABRT_EV4
0493 bool
0494
0495 config CPU_ABRT_EV4T
0496 bool
0497
0498 config CPU_ABRT_LV4T
0499 bool
0500
0501 config CPU_ABRT_EV5T
0502 bool
0503
0504 config CPU_ABRT_EV5TJ
0505 bool
0506
0507 config CPU_ABRT_EV6
0508 bool
0509
0510 config CPU_ABRT_EV7
0511 bool
0512
0513 config CPU_PABRT_LEGACY
0514 bool
0515
0516 config CPU_PABRT_V6
0517 bool
0518
0519 config CPU_PABRT_V7
0520 bool
0521
0522 # The cache model
0523 config CPU_CACHE_V4
0524 bool
0525
0526 config CPU_CACHE_V4WT
0527 bool
0528
0529 config CPU_CACHE_V4WB
0530 bool
0531
0532 config CPU_CACHE_V6
0533 bool
0534
0535 config CPU_CACHE_V7
0536 bool
0537
0538 config CPU_CACHE_NOP
0539 bool
0540
0541 config CPU_CACHE_VIVT
0542 bool
0543
0544 config CPU_CACHE_VIPT
0545 bool
0546
0547 config CPU_CACHE_FA
0548 bool
0549
0550 config CPU_CACHE_V7M
0551 bool
0552
0553 if MMU
0554 # The copy-page model
0555 config CPU_COPY_V4WT
0556 bool
0557
0558 config CPU_COPY_V4WB
0559 bool
0560
0561 config CPU_COPY_FEROCEON
0562 bool
0563
0564 config CPU_COPY_FA
0565 bool
0566
0567 config CPU_COPY_V6
0568 bool
0569
0570 # This selects the TLB model
0571 config CPU_TLB_V4WT
0572 bool
0573 help
0574 ARM Architecture Version 4 TLB with writethrough cache.
0575
0576 config CPU_TLB_V4WB
0577 bool
0578 help
0579 ARM Architecture Version 4 TLB with writeback cache.
0580
0581 config CPU_TLB_V4WBI
0582 bool
0583 help
0584 ARM Architecture Version 4 TLB with writeback cache and invalidate
0585 instruction cache entry.
0586
0587 config CPU_TLB_FEROCEON
0588 bool
0589 help
0590 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
0591
0592 config CPU_TLB_FA
0593 bool
0594 help
0595 Faraday ARM FA526 architecture, unified TLB with writeback cache
0596 and invalidate instruction cache entry. Branch target buffer is
0597 also supported.
0598
0599 config CPU_TLB_V6
0600 bool
0601
0602 config CPU_TLB_V7
0603 bool
0604
0605 endif
0606
0607 config CPU_HAS_ASID
0608 bool
0609 help
0610 This indicates whether the CPU has the ASID register; used to
0611 tag TLB and possibly cache entries.
0612
0613 config CPU_CP15
0614 bool
0615 help
0616 Processor has the CP15 register.
0617
0618 config CPU_CP15_MMU
0619 bool
0620 select CPU_CP15
0621 help
0622 Processor has the CP15 register, which has MMU related registers.
0623
0624 config CPU_CP15_MPU
0625 bool
0626 select CPU_CP15
0627 help
0628 Processor has the CP15 register, which has MPU related registers.
0629
0630 config CPU_USE_DOMAINS
0631 bool
0632 help
0633 This option enables or disables the use of domain switching
0634 using the DACR (domain access control register) to protect memory
0635 domains from each other. In Linux we use three domains: kernel, user
0636 and IO. The domains are used to protect userspace from kernelspace
0637 and to handle IO-space as a special type of memory by assigning
0638 manager or client roles to running code (such as a process).
0639
0640 config CPU_V7M_NUM_IRQ
0641 int "Number of external interrupts connected to the NVIC"
0642 depends on CPU_V7M
0643 default 90 if ARCH_STM32
0644 default 112 if SOC_VF610
0645 default 240
0646 help
0647 This option indicates the number of interrupts connected to the NVIC.
0648 The value can be larger than the real number of interrupts supported
0649 by the system, but must not be lower.
0650 The default value is 240, corresponding to the maximum number of
0651 interrupts supported by the NVIC on Cortex-M family.
0652
0653 If unsure, keep default value.
0654
0655 #
0656 # CPU supports 36-bit I/O
0657 #
0658 config IO_36
0659 bool
0660
0661 comment "Processor Features"
0662
0663 config ARM_LPAE
0664 bool "Support for the Large Physical Address Extension"
0665 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
0666 !CPU_32v4 && !CPU_32v3
0667 select PHYS_ADDR_T_64BIT
0668 select SWIOTLB
0669 help
0670 Say Y if you have an ARMv7 processor supporting the LPAE page
0671 table format and you would like to access memory beyond the
0672 4GB limit. The resulting kernel image will not run on
0673 processors without the LPA extension.
0674
0675 If unsure, say N.
0676
0677 config ARM_PV_FIXUP
0678 def_bool y
0679 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
0680
0681 config ARM_THUMB
0682 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
0683 depends on CPU_THUMB_CAPABLE && !CPU_32v4
0684 default y
0685 help
0686 Say Y if you want to include kernel support for running user space
0687 Thumb binaries.
0688
0689 The Thumb instruction set is a compressed form of the standard ARM
0690 instruction set resulting in smaller binaries at the expense of
0691 slightly less efficient code.
0692
0693 If this option is disabled, and you run userspace that switches to
0694 Thumb mode, signal handling will not work correctly, resulting in
0695 segmentation faults or illegal instruction aborts.
0696
0697 If you don't know what this all is, saying Y is a safe choice.
0698
0699 config ARM_THUMBEE
0700 bool "Enable ThumbEE CPU extension"
0701 depends on CPU_V7
0702 help
0703 Say Y here if you have a CPU with the ThumbEE extension and code to
0704 make use of it. Say N for code that can run on CPUs without ThumbEE.
0705
0706 config ARM_VIRT_EXT
0707 bool
0708 default y if CPU_V7
0709 help
0710 Enable the kernel to make use of the ARM Virtualization
0711 Extensions to install hypervisors without run-time firmware
0712 assistance.
0713
0714 A compliant bootloader is required in order to make maximum
0715 use of this feature. Refer to Documentation/arm/booting.rst for
0716 details.
0717
0718 config SWP_EMULATE
0719 bool "Emulate SWP/SWPB instructions" if !SMP
0720 depends on CPU_V7
0721 default y if SMP
0722 select HAVE_PROC_CPU if PROC_FS
0723 help
0724 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
0725 ARMv7 multiprocessing extensions introduce the ability to disable
0726 these instructions, triggering an undefined instruction exception
0727 when executed. Say Y here to enable software emulation of these
0728 instructions for userspace (not kernel) using LDREX/STREX.
0729 Also creates /proc/cpu/swp_emulation for statistics.
0730
0731 In some older versions of glibc [<=2.8] SWP is used during futex
0732 trylock() operations with the assumption that the code will not
0733 be preempted. This invalid assumption may be more likely to fail
0734 with SWP emulation enabled, leading to deadlock of the user
0735 application.
0736
0737 NOTE: when accessing uncached shared regions, LDREX/STREX rely
0738 on an external transaction monitoring block called a global
0739 monitor to maintain update atomicity. If your system does not
0740 implement a global monitor, this option can cause programs that
0741 perform SWP operations to uncached memory to deadlock.
0742
0743 If unsure, say Y.
0744
0745 choice
0746 prompt "CPU Endianess"
0747 default CPU_LITTLE_ENDIAN
0748
0749 config CPU_LITTLE_ENDIAN
0750 bool "Built little-endian kernel"
0751 help
0752 Say Y if you plan on running a kernel in little-endian mode.
0753 This is the default and is used in practically all modern user
0754 space builds.
0755
0756 config CPU_BIG_ENDIAN
0757 bool "Build big-endian kernel"
0758 depends on !LD_IS_LLD
0759 help
0760 Say Y if you plan on running a kernel in big-endian mode.
0761 This works on many machines using ARMv6 or newer processors
0762 but requires big-endian user space.
0763
0764 The only ARMv5 platform with big-endian support is
0765 Intel IXP4xx.
0766
0767 endchoice
0768
0769 config CPU_ENDIAN_BE8
0770 bool
0771 depends on CPU_BIG_ENDIAN
0772 default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
0773 help
0774 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
0775
0776 config CPU_ENDIAN_BE32
0777 bool
0778 depends on CPU_BIG_ENDIAN
0779 default !CPU_ENDIAN_BE8
0780 help
0781 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
0782
0783 config CPU_HIGH_VECTOR
0784 depends on !MMU && CPU_CP15 && !CPU_ARM740T
0785 bool "Select the High exception vector"
0786 help
0787 Say Y here to select high exception vector(0xFFFF0000~).
0788 The exception vector can vary depending on the platform
0789 design in nommu mode. If your platform needs to select
0790 high exception vector, say Y.
0791 Otherwise or if you are unsure, say N, and the low exception
0792 vector (0x00000000~) will be used.
0793
0794 config CPU_ICACHE_DISABLE
0795 bool "Disable I-Cache (I-bit)"
0796 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
0797 help
0798 Say Y here to disable the processor instruction cache. Unless
0799 you have a reason not to or are unsure, say N.
0800
0801 config CPU_ICACHE_MISMATCH_WORKAROUND
0802 bool "Workaround for I-Cache line size mismatch between CPU cores"
0803 depends on SMP && CPU_V7
0804 help
0805 Some big.LITTLE systems have I-Cache line size mismatch between
0806 LITTLE and big cores. Say Y here to enable a workaround for
0807 proper I-Cache support on such systems. If unsure, say N.
0808
0809 config CPU_DCACHE_DISABLE
0810 bool "Disable D-Cache (C-bit)"
0811 depends on (CPU_CP15 && !SMP) || CPU_V7M
0812 help
0813 Say Y here to disable the processor data cache. Unless
0814 you have a reason not to or are unsure, say N.
0815
0816 config CPU_DCACHE_SIZE
0817 hex
0818 depends on CPU_ARM740T || CPU_ARM946E
0819 default 0x00001000 if CPU_ARM740T
0820 default 0x00002000 # default size for ARM946E-S
0821 help
0822 Some cores are synthesizable to have various sized cache. For
0823 ARM946E-S case, it can vary from 0KB to 1MB.
0824 To support such cache operations, it is efficient to know the size
0825 before compile time.
0826 If your SoC is configured to have a different size, define the value
0827 here with proper conditions.
0828
0829 config CPU_DCACHE_WRITETHROUGH
0830 bool "Force write through D-cache"
0831 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
0832 default y if CPU_ARM925T
0833 help
0834 Say Y here to use the data cache in writethrough mode. Unless you
0835 specifically require this or are unsure, say N.
0836
0837 config CPU_CACHE_ROUND_ROBIN
0838 bool "Round robin I and D cache replacement algorithm"
0839 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
0840 help
0841 Say Y here to use the predictable round-robin cache replacement
0842 policy. Unless you specifically require this or are unsure, say N.
0843
0844 config CPU_BPREDICT_DISABLE
0845 bool "Disable branch prediction"
0846 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
0847 help
0848 Say Y here to disable branch prediction. If unsure, say N.
0849
0850 config CPU_SPECTRE
0851 bool
0852 select GENERIC_CPU_VULNERABILITIES
0853
0854 config HARDEN_BRANCH_PREDICTOR
0855 bool "Harden the branch predictor against aliasing attacks" if EXPERT
0856 depends on CPU_SPECTRE
0857 default y
0858 help
0859 Speculation attacks against some high-performance processors rely
0860 on being able to manipulate the branch predictor for a victim
0861 context by executing aliasing branches in the attacker context.
0862 Such attacks can be partially mitigated against by clearing
0863 internal branch predictor state and limiting the prediction
0864 logic in some situations.
0865
0866 This config option will take CPU-specific actions to harden
0867 the branch predictor against aliasing attacks and may rely on
0868 specific instruction sequences or control bits being set by
0869 the system firmware.
0870
0871 If unsure, say Y.
0872
0873 config HARDEN_BRANCH_HISTORY
0874 bool "Harden Spectre style attacks against branch history" if EXPERT
0875 depends on CPU_SPECTRE
0876 default y
0877 help
0878 Speculation attacks against some high-performance processors can
0879 make use of branch history to influence future speculation. When
0880 taking an exception, a sequence of branches overwrites the branch
0881 history, or branch history is invalidated.
0882
0883 config TLS_REG_EMUL
0884 bool
0885 select NEED_KUSER_HELPERS
0886 help
0887 An SMP system using a pre-ARMv6 processor (there are apparently
0888 a few prototypes like that in existence) and therefore access to
0889 that required register must be emulated.
0890
0891 config NEED_KUSER_HELPERS
0892 bool
0893
0894 config KUSER_HELPERS
0895 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
0896 depends on MMU
0897 default y
0898 help
0899 Warning: disabling this option may break user programs.
0900
0901 Provide kuser helpers in the vector page. The kernel provides
0902 helper code to userspace in read only form at a fixed location
0903 in the high vector page to allow userspace to be independent of
0904 the CPU type fitted to the system. This permits binaries to be
0905 run on ARMv4 through to ARMv7 without modification.
0906
0907 See Documentation/arm/kernel_user_helpers.rst for details.
0908
0909 However, the fixed address nature of these helpers can be used
0910 by ROP (return orientated programming) authors when creating
0911 exploits.
0912
0913 If all of the binaries and libraries which run on your platform
0914 are built specifically for your platform, and make no use of
0915 these helpers, then you can turn this option off to hinder
0916 such exploits. However, in that case, if a binary or library
0917 relying on those helpers is run, it will receive a SIGILL signal,
0918 which will terminate the program.
0919
0920 Say N here only if you are absolutely certain that you do not
0921 need these helpers; otherwise, the safe option is to say Y.
0922
0923 config VDSO
0924 bool "Enable VDSO for acceleration of some system calls"
0925 depends on AEABI && MMU && CPU_V7
0926 default y if ARM_ARCH_TIMER
0927 select HAVE_GENERIC_VDSO
0928 select GENERIC_TIME_VSYSCALL
0929 select GENERIC_VDSO_32
0930 select GENERIC_GETTIMEOFDAY
0931 help
0932 Place in the process address space an ELF shared object
0933 providing fast implementations of gettimeofday and
0934 clock_gettime. Systems that implement the ARM architected
0935 timer will receive maximum benefit.
0936
0937 You must have glibc 2.22 or later for programs to seamlessly
0938 take advantage of this.
0939
0940 config DMA_CACHE_RWFO
0941 bool "Enable read/write for ownership DMA cache maintenance"
0942 depends on CPU_V6K && SMP
0943 default y
0944 help
0945 The Snoop Control Unit on ARM11MPCore does not detect the
0946 cache maintenance operations and the dma_{map,unmap}_area()
0947 functions may leave stale cache entries on other CPUs. By
0948 enabling this option, Read or Write For Ownership in the ARMv6
0949 DMA cache maintenance functions is performed. These LDR/STR
0950 instructions change the cache line state to shared or modified
0951 so that the cache operation has the desired effect.
0952
0953 Note that the workaround is only valid on processors that do
0954 not perform speculative loads into the D-cache. For such
0955 processors, if cache maintenance operations are not broadcast
0956 in hardware, other workarounds are needed (e.g. cache
0957 maintenance broadcasting in software via FIQ).
0958
0959 config OUTER_CACHE
0960 bool
0961
0962 config OUTER_CACHE_SYNC
0963 bool
0964 select ARM_HEAVY_MB
0965 help
0966 The outer cache has a outer_cache_fns.sync function pointer
0967 that can be used to drain the write buffer of the outer cache.
0968
0969 config CACHE_B15_RAC
0970 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
0971 depends on ARCH_BRCMSTB
0972 default y
0973 help
0974 This option enables the Broadcom Brahma-B15 read-ahead cache
0975 controller. If disabled, the read-ahead cache remains off.
0976
0977 config CACHE_FEROCEON_L2
0978 bool "Enable the Feroceon L2 cache controller"
0979 depends on ARCH_MV78XX0 || ARCH_MVEBU
0980 default y
0981 select OUTER_CACHE
0982 help
0983 This option enables the Feroceon L2 cache controller.
0984
0985 config CACHE_FEROCEON_L2_WRITETHROUGH
0986 bool "Force Feroceon L2 cache write through"
0987 depends on CACHE_FEROCEON_L2
0988 help
0989 Say Y here to use the Feroceon L2 cache in writethrough mode.
0990 Unless you specifically require this, say N for writeback mode.
0991
0992 config MIGHT_HAVE_CACHE_L2X0
0993 bool
0994 help
0995 This option should be selected by machines which have a L2x0
0996 or PL310 cache controller, but where its use is optional.
0997
0998 The only effect of this option is to make CACHE_L2X0 and
0999 related options available to the user for configuration.
1000
1001 Boards or SoCs which always require the cache controller
1002 support to be present should select CACHE_L2X0 directly
1003 instead of this option, thus preventing the user from
1004 inadvertently configuring a broken kernel.
1005
1006 config CACHE_L2X0
1007 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
1008 default MIGHT_HAVE_CACHE_L2X0
1009 select OUTER_CACHE
1010 select OUTER_CACHE_SYNC
1011 help
1012 This option enables the L2x0 PrimeCell.
1013
1014 config CACHE_L2X0_PMU
1015 bool "L2x0 performance monitor support" if CACHE_L2X0
1016 depends on PERF_EVENTS
1017 help
1018 This option enables support for the performance monitoring features
1019 of the L220 and PL310 outer cache controllers.
1020
1021 if CACHE_L2X0
1022
1023 config PL310_ERRATA_588369
1024 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1025 help
1026 The PL310 L2 cache controller implements three types of Clean &
1027 Invalidate maintenance operations: by Physical Address
1028 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1029 They are architecturally defined to behave as the execution of a
1030 clean operation followed immediately by an invalidate operation,
1031 both performing to the same memory location. This functionality
1032 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1033 as clean lines are not invalidated as a result of these operations.
1034
1035 config PL310_ERRATA_727915
1036 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1037 help
1038 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1039 operation (offset 0x7FC). This operation runs in background so that
1040 PL310 can handle normal accesses while it is in progress. Under very
1041 rare circumstances, due to this erratum, write data can be lost when
1042 PL310 treats a cacheable write transaction during a Clean &
1043 Invalidate by Way operation. Revisions prior to r3p1 are affected by
1044 this errata (fixed in r3p1).
1045
1046 config PL310_ERRATA_753970
1047 bool "PL310 errata: cache sync operation may be faulty"
1048 help
1049 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1050
1051 Under some condition the effect of cache sync operation on
1052 the store buffer still remains when the operation completes.
1053 This means that the store buffer is always asked to drain and
1054 this prevents it from merging any further writes. The workaround
1055 is to replace the normal offset of cache sync operation (0x730)
1056 by another offset targeting an unmapped PL310 register 0x740.
1057 This has the same effect as the cache sync operation: store buffer
1058 drain and waiting for all buffers empty.
1059
1060 config PL310_ERRATA_769419
1061 bool "PL310 errata: no automatic Store Buffer drain"
1062 help
1063 On revisions of the PL310 prior to r3p2, the Store Buffer does
1064 not automatically drain. This can cause normal, non-cacheable
1065 writes to be retained when the memory system is idle, leading
1066 to suboptimal I/O performance for drivers using coherent DMA.
1067 This option adds a write barrier to the cpu_idle loop so that,
1068 on systems with an outer cache, the store buffer is drained
1069 explicitly.
1070
1071 endif
1072
1073 config CACHE_TAUROS2
1074 bool "Enable the Tauros2 L2 cache controller"
1075 depends on (CPU_MOHAWK || CPU_PJ4)
1076 default y
1077 select OUTER_CACHE
1078 help
1079 This option enables the Tauros2 L2 cache controller (as
1080 found on PJ1/PJ4).
1081
1082 config CACHE_UNIPHIER
1083 bool "Enable the UniPhier outer cache controller"
1084 depends on ARCH_UNIPHIER
1085 select ARM_L1_CACHE_SHIFT_7
1086 select OUTER_CACHE
1087 select OUTER_CACHE_SYNC
1088 help
1089 This option enables the UniPhier outer cache (system cache)
1090 controller.
1091
1092 config CACHE_XSC3L2
1093 bool "Enable the L2 cache on XScale3"
1094 depends on CPU_XSC3
1095 default y
1096 select OUTER_CACHE
1097 help
1098 This option enables the L2 cache on XScale3.
1099
1100 config ARM_L1_CACHE_SHIFT_6
1101 bool
1102 default y if CPU_V7
1103 help
1104 Setting ARM L1 cache line size to 64 Bytes.
1105
1106 config ARM_L1_CACHE_SHIFT_7
1107 bool
1108 help
1109 Setting ARM L1 cache line size to 128 Bytes.
1110
1111 config ARM_L1_CACHE_SHIFT
1112 int
1113 default 7 if ARM_L1_CACHE_SHIFT_7
1114 default 6 if ARM_L1_CACHE_SHIFT_6
1115 default 5
1116
1117 config ARM_DMA_MEM_BUFFERABLE
1118 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1119 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1120 help
1121 Historically, the kernel has used strongly ordered mappings to
1122 provide DMA coherent memory. With the advent of ARMv7, mapping
1123 memory with differing types results in unpredictable behaviour,
1124 so on these CPUs, this option is forced on.
1125
1126 Multiple mappings with differing attributes is also unpredictable
1127 on ARMv6 CPUs, but since they do not have aggressive speculative
1128 prefetch, no harm appears to occur.
1129
1130 However, drivers may be missing the necessary barriers for ARMv6,
1131 and therefore turning this on may result in unpredictable driver
1132 behaviour. Therefore, we offer this as an option.
1133
1134 On some of the beefier ARMv7-M machines (with DMA and write
1135 buffers) you likely want this enabled, while those that
1136 didn't need it until now also won't need it in the future.
1137
1138 You are recommended say 'Y' here and debug any affected drivers.
1139
1140 config ARM_HEAVY_MB
1141 bool
1142
1143 config DEBUG_ALIGN_RODATA
1144 bool "Make rodata strictly non-executable"
1145 depends on STRICT_KERNEL_RWX
1146 default y
1147 help
1148 If this is set, rodata will be made explicitly non-executable. This
1149 provides protection on the rare chance that attackers might find and
1150 use ROP gadgets that exist in the rodata section. This adds an
1151 additional section-aligned split of rodata from kernel text so it
1152 can be made explicitly non-executable. This padding may waste memory
1153 space to gain the additional protection.
