arm/mach-zynq/pm.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Zynq power management
0004  *
0005  *  Copyright (C) 2012 - 2014 Xilinx
0006  *
0007  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
0008  */
0009
0010 #include <linux/io.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_device.h>
0013 #include "common.h"
0014
0015 /* register offsets */
0016 #define DDRC_CTRL_REG1_OFFS     0x60
0017 #define DDRC_DRAM_PARAM_REG3_OFFS   0x20
0018
0019 /* bitfields */
0020 #define DDRC_CLOCKSTOP_MASK BIT(23)
0021 #define DDRC_SELFREFRESH_MASK   BIT(12)
0022
0023 static void __iomem *ddrc_base;
0024
0025 /**
0026  * zynq_pm_ioremap() - Create IO mappings
0027  * @comp:   DT compatible string
0028  * Return: Pointer to the mapped memory or NULL.
0029  *
0030  * Remap the memory region for a compatible DT node.
0031  */
0032 static void __iomem *zynq_pm_ioremap(const char *comp)
0033 {
0034     struct device_node *np;
0035     void __iomem *base = NULL;
0036
0037     np = of_find_compatible_node(NULL, NULL, comp);
0038     if (np) {
0039         base = of_iomap(np, 0);
0040         of_node_put(np);
0041     } else {
0042         pr_warn("%s: no compatible node found for '%s'\n", __func__,
0043                 comp);
0044     }
0045
0046     return base;
0047 }
0048
0049 /**
0050  * zynq_pm_late_init() - Power management init
0051  *
0052  * Initialization of power management related features and infrastructure.
0053  */
0054 void __init zynq_pm_late_init(void)
0055 {
0056     u32 reg;
0057
0058     ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05");
0059     if (!ddrc_base) {
0060         pr_warn("%s: Unable to map DDRC IO memory.\n", __func__);
0061     } else {
0062         /*
0063          * Enable DDRC clock stop feature. The HW takes care of
0064          * entering/exiting the correct mode depending
0065          * on activity state.
0066          */
0067         reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
0068         reg |= DDRC_CLOCKSTOP_MASK;
0069         writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
0070     }
0071 }