arm/mach-zynq/common.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * This file contains common function prototypes to avoid externs
0004  * in the c files.
0005  *
0006  *  Copyright (C) 2011 Xilinx
0007  */
0008
0009 #ifndef __MACH_ZYNQ_COMMON_H__
0010 #define __MACH_ZYNQ_COMMON_H__
0011
0012 extern int zynq_slcr_init(void);
0013 extern int zynq_early_slcr_init(void);
0014 extern void zynq_slcr_cpu_stop(int cpu);
0015 extern void zynq_slcr_cpu_start(int cpu);
0016 extern bool zynq_slcr_cpu_state_read(int cpu);
0017 extern void zynq_slcr_cpu_state_write(int cpu, bool die);
0018 extern u32 zynq_slcr_get_device_id(void);
0019
0020 #ifdef CONFIG_SMP
0021 extern char zynq_secondary_trampoline;
0022 extern char zynq_secondary_trampoline_jump;
0023 extern char zynq_secondary_trampoline_end;
0024 extern int zynq_cpun_start(u32 address, int cpu);
0025 extern const struct smp_operations zynq_smp_ops;
0026 #endif
0027
0028 extern void __iomem *zynq_scu_base;
0029
0030 void zynq_pm_late_init(void);
0031
0032 static inline void zynq_core_pm_init(void)
0033 {
0034     /* A9 clock gating */
0035     asm volatile ("mrc  p15, 0, r12, c15, c0, 0\n"
0036               "orr  r12, r12, #1\n"
0037               "mcr  p15, 0, r12, c15, c0, 0\n"
0038               : /* no outputs */
0039               : /* no inputs */
0040               : "r12");
0041 }
0042
0043 #endif