arm/mach-zynq/common.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * This file contains common code that is intended to be used across
0004  * boards so that it's not replicated.
0005  *
0006  *  Copyright (C) 2011 Xilinx
0007  */
0008
0009 #include <linux/init.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/cpumask.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/clk.h>
0015 #include <linux/clk/zynq.h>
0016 #include <linux/clocksource.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_clk.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/of_platform.h>
0021 #include <linux/of.h>
0022 #include <linux/memblock.h>
0023 #include <linux/irqchip.h>
0024 #include <linux/irqchip/arm-gic.h>
0025 #include <linux/slab.h>
0026 #include <linux/sys_soc.h>
0027 #include <linux/pgtable.h>
0028
0029 #include <asm/mach/arch.h>
0030 #include <asm/mach/map.h>
0031 #include <asm/mach/time.h>
0032 #include <asm/mach-types.h>
0033 #include <asm/page.h>
0034 #include <asm/smp_scu.h>
0035 #include <asm/system_info.h>
0036 #include <asm/hardware/cache-l2x0.h>
0037
0038 #include "common.h"
0039
0040 #define ZYNQ_DEVCFG_MCTRL       0x80
0041 #define ZYNQ_DEVCFG_PS_VERSION_SHIFT    28
0042 #define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF
0043
0044 void __iomem *zynq_scu_base;
0045
0046 /**
0047  * zynq_memory_init - Initialize special memory
0048  *
0049  * We need to stop things allocating the low memory as DMA can't work in
0050  * the 1st 512K of memory.
0051  */
0052 static void __init zynq_memory_init(void)
0053 {
0054     if (!__pa(PAGE_OFFSET))
0055         memblock_reserve(__pa(PAGE_OFFSET), 0x80000);
0056 }
0057
0058 static struct platform_device zynq_cpuidle_device = {
0059     .name = "cpuidle-zynq",
0060 };
0061
0062 /**
0063  * zynq_get_revision - Get Zynq silicon revision
0064  *
0065  * Return: Silicon version or -1 otherwise
0066  */
0067 static int __init zynq_get_revision(void)
0068 {
0069     struct device_node *np;
0070     void __iomem *zynq_devcfg_base;
0071     u32 revision;
0072
0073     np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0");
0074     if (!np) {
0075         pr_err("%s: no devcfg node found\n", __func__);
0076         return -1;
0077     }
0078
0079     zynq_devcfg_base = of_iomap(np, 0);
0080     of_node_put(np);
0081     if (!zynq_devcfg_base) {
0082         pr_err("%s: Unable to map I/O memory\n", __func__);
0083         return -1;
0084     }
0085
0086     revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL);
0087     revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT;
0088     revision &= ZYNQ_DEVCFG_PS_VERSION_MASK;
0089
0090     iounmap(zynq_devcfg_base);
0091
0092     return revision;
0093 }
0094
0095 static void __init zynq_init_late(void)
0096 {
0097     zynq_core_pm_init();
0098     zynq_pm_late_init();
0099 }
0100
0101 /**
0102  * zynq_init_machine - System specific initialization, intended to be
0103  *             called from board specific initialization.
0104  */
0105 static void __init zynq_init_machine(void)
0106 {
0107     struct soc_device_attribute *soc_dev_attr;
0108     struct soc_device *soc_dev;
0109     struct device *parent = NULL;
0110
0111     soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
0112     if (!soc_dev_attr)
0113         goto out;
0114
0115     system_rev = zynq_get_revision();
0116
0117     soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq");
0118     soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev);
0119     soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x",
0120                      zynq_slcr_get_device_id());
0121
0122     soc_dev = soc_device_register(soc_dev_attr);
0123     if (IS_ERR(soc_dev)) {
0124         kfree(soc_dev_attr->family);
0125         kfree(soc_dev_attr->revision);
0126         kfree(soc_dev_attr->soc_id);
0127         kfree(soc_dev_attr);
0128         goto out;
0129     }
0130
0131     parent = soc_device_to_device(soc_dev);
0132
0133 out:
0134     /*
0135      * Finished with the static registrations now; fill in the missing
0136      * devices
0137      */
0138     of_platform_default_populate(NULL, NULL, parent);
0139
0140     platform_device_register(&zynq_cpuidle_device);
0141 }
0142
0143 static void __init zynq_timer_init(void)
0144 {
0145     zynq_clock_init();
0146     of_clk_init(NULL);
0147     timer_probe();
0148 }
0149
0150 static struct map_desc zynq_cortex_a9_scu_map __initdata = {
0151     .length = SZ_256,
0152     .type   = MT_DEVICE,
0153 };
0154
0155 static void __init zynq_scu_map_io(void)
0156 {
0157     unsigned long base;
0158
0159     base = scu_a9_get_base();
0160     zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base);
0161     /* Expected address is in vmalloc area that's why simple assign here */
0162     zynq_cortex_a9_scu_map.virtual = base;
0163     iotable_init(&zynq_cortex_a9_scu_map, 1);
0164     zynq_scu_base = (void __iomem *)base;
0165     BUG_ON(!zynq_scu_base);
0166 }
0167
0168 /**
0169  * zynq_map_io - Create memory mappings needed for early I/O.
0170  */
0171 static void __init zynq_map_io(void)
0172 {
0173     debug_ll_io_init();
0174     zynq_scu_map_io();
0175 }
0176
0177 static void __init zynq_irq_init(void)
0178 {
0179     zynq_early_slcr_init();
0180     irqchip_init();
0181 }
0182
0183 static const char * const zynq_dt_match[] = {
0184     "xlnx,zynq-7000",
0185     NULL
0186 };
0187
0188 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
0189     /* 64KB way size, 8-way associativity, parity disabled */
0190     .l2c_aux_val    = 0x00400000,
0191     .l2c_aux_mask   = 0xffbfffff,
0192     .smp        = smp_ops(zynq_smp_ops),
0193     .map_io     = zynq_map_io,
0194     .init_irq   = zynq_irq_init,
0195     .init_machine   = zynq_init_machine,
0196     .init_late  = zynq_init_late,
0197     .init_time  = zynq_timer_init,
0198     .dt_compat  = zynq_dt_match,
0199     .reserve    = zynq_memory_init,
0200 MACHINE_END