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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Versatile Express Serial Power Controller (SPC) support
0004  *
0005  * Copyright (C) 2013 ARM Ltd.
0006  *
0007  * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
0008  *          Achin Gupta           <achin.gupta@arm.com>
0009  *          Lorenzo Pieralisi     <lorenzo.pieralisi@arm.com>
0010  */
0011 
0012 #include <linux/clk-provider.h>
0013 #include <linux/clkdev.h>
0014 #include <linux/cpu.h>
0015 #include <linux/delay.h>
0016 #include <linux/err.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/pm_opp.h>
0021 #include <linux/slab.h>
0022 #include <linux/semaphore.h>
0023 
0024 #include <asm/cacheflush.h>
0025 
0026 #include "spc.h"
0027 
0028 #define SPCLOG "vexpress-spc: "
0029 
0030 #define PERF_LVL_A15        0x00
0031 #define PERF_REQ_A15        0x04
0032 #define PERF_LVL_A7     0x08
0033 #define PERF_REQ_A7     0x0c
0034 #define COMMS           0x10
0035 #define COMMS_REQ       0x14
0036 #define PWC_STATUS      0x18
0037 #define PWC_FLAG        0x1c
0038 
0039 /* SPC wake-up IRQs status and mask */
0040 #define WAKE_INT_MASK       0x24
0041 #define WAKE_INT_RAW        0x28
0042 #define WAKE_INT_STAT       0x2c
0043 /* SPC power down registers */
0044 #define A15_PWRDN_EN        0x30
0045 #define A7_PWRDN_EN     0x34
0046 /* SPC per-CPU mailboxes */
0047 #define A15_BX_ADDR0        0x68
0048 #define A7_BX_ADDR0     0x78
0049 
0050 /* SPC CPU/cluster reset statue */
0051 #define STANDBYWFI_STAT     0x3c
0052 #define STANDBYWFI_STAT_A15_CPU_MASK(cpu)   (1 << (cpu))
0053 #define STANDBYWFI_STAT_A7_CPU_MASK(cpu)    (1 << (3 + (cpu)))
0054 
0055 /* SPC system config interface registers */
0056 #define SYSCFG_WDATA        0x70
0057 #define SYSCFG_RDATA        0x74
0058 
0059 /* A15/A7 OPP virtual register base */
0060 #define A15_PERFVAL_BASE    0xC10
0061 #define A7_PERFVAL_BASE     0xC30
0062 
0063 /* Config interface control bits */
0064 #define SYSCFG_START        BIT(31)
0065 #define SYSCFG_SCC      (6 << 20)
0066 #define SYSCFG_STAT     (14 << 20)
0067 
0068 /* wake-up interrupt masks */
0069 #define GBL_WAKEUP_INT_MSK  (0x3 << 10)
0070 
0071 /* TC2 static dual-cluster configuration */
0072 #define MAX_CLUSTERS        2
0073 
0074 /*
0075  * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
0076  * operation, the operation could start just before jiffie is about
0077  * to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz
0078  */
0079 #define TIMEOUT_US  20000
0080 
0081 #define MAX_OPPS    8
0082 #define CA15_DVFS   0
0083 #define CA7_DVFS    1
0084 #define SPC_SYS_CFG 2
0085 #define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
0086 #define STAT_ERR(type)      ((1 << 1) << (type << 2))
0087 #define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type))
0088 
0089 struct ve_spc_opp {
0090     unsigned long freq;
0091     unsigned long u_volt;
0092 };
0093 
0094 struct ve_spc_drvdata {
0095     void __iomem *baseaddr;
0096     /*
0097      * A15s cluster identifier
0098      * It corresponds to A15 processors MPIDR[15:8] bitfield
0099      */
0100     u32 a15_clusid;
0101     uint32_t cur_rsp_mask;
0102     uint32_t cur_rsp_stat;
0103     struct semaphore sem;
0104     struct completion done;
0105     struct ve_spc_opp *opps[MAX_CLUSTERS];
0106     int num_opps[MAX_CLUSTERS];
0107 };
0108 
0109 static struct ve_spc_drvdata *info;
0110 
0111 static inline bool cluster_is_a15(u32 cluster)
0112 {
0113     return cluster == info->a15_clusid;
0114 }
0115 
0116 /**
0117  * ve_spc_global_wakeup_irq() - sets/clears global wakeup IRQs
0118  *
0119  * @set: if true, global wake-up IRQs are set, if false they are cleared
0120  *
0121  * Function to set/clear global wakeup IRQs. Not protected by locking since
0122  * it might be used in code paths where normal cacheable locks are not
0123  * working. Locking must be provided by the caller to ensure atomicity.
0124  */
0125 void ve_spc_global_wakeup_irq(bool set)
0126 {
0127     u32 reg;
0128 
0129     reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
0130 
0131     if (set)
0132         reg |= GBL_WAKEUP_INT_MSK;
0133     else
0134         reg &= ~GBL_WAKEUP_INT_MSK;
0135 
0136     writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
0137 }
0138 
0139 /**
0140  * ve_spc_cpu_wakeup_irq() - sets/clears per-CPU wake-up IRQs
0141  *
0142  * @cluster: mpidr[15:8] bitfield describing cluster affinity level
0143  * @cpu: mpidr[7:0] bitfield describing cpu affinity level
0144  * @set: if true, wake-up IRQs are set, if false they are cleared
0145  *
0146  * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
0147  * it might be used in code paths where normal cacheable locks are not
0148  * working. Locking must be provided by the caller to ensure atomicity.
0149  */
0150 void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
0151 {
0152     u32 mask, reg;
0153 
0154     if (cluster >= MAX_CLUSTERS)
0155         return;
0156 
0157     mask = BIT(cpu);
0158 
0159     if (!cluster_is_a15(cluster))
0160         mask <<= 4;
0161 
0162     reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
0163 
0164     if (set)
0165         reg |= mask;
0166     else
0167         reg &= ~mask;
0168 
0169     writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
0170 }
0171 
0172 /**
0173  * ve_spc_set_resume_addr() - set the jump address used for warm boot
0174  *
0175  * @cluster: mpidr[15:8] bitfield describing cluster affinity level
0176  * @cpu: mpidr[7:0] bitfield describing cpu affinity level
0177  * @addr: physical resume address
0178  */
0179 void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
0180 {
0181     void __iomem *baseaddr;
0182 
0183     if (cluster >= MAX_CLUSTERS)
0184         return;
0185 
0186     if (cluster_is_a15(cluster))
0187         baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
0188     else
0189         baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
0190 
0191     writel_relaxed(addr, baseaddr);
0192 }
0193 
0194 /**
0195  * ve_spc_powerdown() - enables/disables cluster powerdown
0196  *
0197  * @cluster: mpidr[15:8] bitfield describing cluster affinity level
0198  * @enable: if true enables powerdown, if false disables it
0199  *
0200  * Function to enable/disable cluster powerdown. Not protected by locking
0201  * since it might be used in code paths where normal cacheable locks are not
0202  * working. Locking must be provided by the caller to ensure atomicity.
0203  */
0204 void ve_spc_powerdown(u32 cluster, bool enable)
0205 {
0206     u32 pwdrn_reg;
0207 
0208     if (cluster >= MAX_CLUSTERS)
0209         return;
0210 
0211     pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
0212     writel_relaxed(enable, info->baseaddr + pwdrn_reg);
0213 }
0214 
0215 static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
0216 {
0217     return cluster_is_a15(cluster) ?
0218           STANDBYWFI_STAT_A15_CPU_MASK(cpu)
0219         : STANDBYWFI_STAT_A7_CPU_MASK(cpu);
0220 }
0221 
0222 /**
0223  * ve_spc_cpu_in_wfi() - Checks if the specified CPU is in WFI or not
0224  *
0225  * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
0226  * @cluster: mpidr[15:8] bitfield describing cluster affinity level
0227  *
0228  * @return: non-zero if and only if the specified CPU is in WFI
0229  *
0230  * Take care when interpreting the result of this function: a CPU might
0231  * be in WFI temporarily due to idle, and is not necessarily safely
0232  * parked.
0233  */
0234 int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
0235 {
0236     int ret;
0237     u32 mask = standbywfi_cpu_mask(cpu, cluster);
0238 
0239     if (cluster >= MAX_CLUSTERS)
0240         return 1;
0241 
0242     ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);
0243 
0244     pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
0245          __func__, STANDBYWFI_STAT, ret, mask);
0246 
0247     return ret & mask;
0248 }
0249 
0250 static int ve_spc_get_performance(int cluster, u32 *freq)
0251 {
0252     struct ve_spc_opp *opps = info->opps[cluster];
0253     u32 perf_cfg_reg = 0;
0254     u32 perf;
0255 
0256     perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7;
0257 
0258     perf = readl_relaxed(info->baseaddr + perf_cfg_reg);
0259     if (perf >= info->num_opps[cluster])
0260         return -EINVAL;
0261 
0262     opps += perf;
0263     *freq = opps->freq;
0264 
0265     return 0;
0266 }
0267 
0268 /* find closest match to given frequency in OPP table */
0269 static int ve_spc_round_performance(int cluster, u32 freq)
0270 {
0271     int idx, max_opp = info->num_opps[cluster];
0272     struct ve_spc_opp *opps = info->opps[cluster];
0273     u32 fmin = 0, fmax = ~0, ftmp;
0274 
0275     freq /= 1000; /* OPP entries in kHz */
0276     for (idx = 0; idx < max_opp; idx++, opps++) {
0277         ftmp = opps->freq;
0278         if (ftmp >= freq) {
0279             if (ftmp <= fmax)
0280                 fmax = ftmp;
0281         } else {
0282             if (ftmp >= fmin)
0283                 fmin = ftmp;
0284         }
0285     }
0286     if (fmax != ~0)
0287         return fmax * 1000;
0288     else
0289         return fmin * 1000;
0290 }
0291 
0292 static int ve_spc_find_performance_index(int cluster, u32 freq)
0293 {
0294     int idx, max_opp = info->num_opps[cluster];
0295     struct ve_spc_opp *opps = info->opps[cluster];
0296 
0297     for (idx = 0; idx < max_opp; idx++, opps++)
0298         if (opps->freq == freq)
0299             break;
0300     return (idx == max_opp) ? -EINVAL : idx;
0301 }
0302 
0303 static int ve_spc_waitforcompletion(int req_type)
0304 {
0305     int ret = wait_for_completion_interruptible_timeout(
0306             &info->done, usecs_to_jiffies(TIMEOUT_US));
0307     if (ret == 0)
0308         ret = -ETIMEDOUT;
0309     else if (ret > 0)
0310         ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO;
0311     return ret;
0312 }
0313 
0314 static int ve_spc_set_performance(int cluster, u32 freq)
0315 {
0316     u32 perf_cfg_reg;
0317     int ret, perf, req_type;
0318 
0319     if (cluster_is_a15(cluster)) {
0320         req_type = CA15_DVFS;
0321         perf_cfg_reg = PERF_LVL_A15;
0322     } else {
0323         req_type = CA7_DVFS;
0324         perf_cfg_reg = PERF_LVL_A7;
0325     }
0326 
0327     perf = ve_spc_find_performance_index(cluster, freq);
0328 
0329     if (perf < 0)
0330         return perf;
0331 
0332     if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
0333         return -ETIME;
0334 
0335     init_completion(&info->done);
0336     info->cur_rsp_mask = RESPONSE_MASK(req_type);
0337 
0338     writel(perf, info->baseaddr + perf_cfg_reg);
0339     ret = ve_spc_waitforcompletion(req_type);
0340 
0341     info->cur_rsp_mask = 0;
0342     up(&info->sem);
0343 
0344     return ret;
0345 }
0346 
0347 static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data)
0348 {
0349     int ret;
0350 
0351     if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
0352         return -ETIME;
0353 
0354     init_completion(&info->done);
0355     info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG);
0356 
0357     /* Set the control value */
0358     writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS);
0359     ret = ve_spc_waitforcompletion(SPC_SYS_CFG);
0360 
0361     if (ret == 0)
0362         *data = readl(info->baseaddr + SYSCFG_RDATA);
0363 
0364     info->cur_rsp_mask = 0;
0365     up(&info->sem);
0366 
0367     return ret;
0368 }
0369 
0370 static irqreturn_t ve_spc_irq_handler(int irq, void *data)
0371 {
0372     struct ve_spc_drvdata *drv_data = data;
0373     uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS);
0374 
0375     if (info->cur_rsp_mask & status) {
0376         info->cur_rsp_stat = status;
0377         complete(&drv_data->done);
0378     }
0379 
0380     return IRQ_HANDLED;
0381 }
0382 
0383 /*
0384  *  +--------------------------+
0385  *  | 31      20 | 19        0 |
0386  *  +--------------------------+
0387  *  |   m_volt   |  freq(kHz)  |
0388  *  +--------------------------+
0389  */
0390 #define MULT_FACTOR 20
0391 #define VOLT_SHIFT  20
0392 #define FREQ_MASK   (0xFFFFF)
0393 static int ve_spc_populate_opps(uint32_t cluster)
0394 {
0395     uint32_t data = 0, off, ret, idx;
0396     struct ve_spc_opp *opps;
0397 
0398     opps = kcalloc(MAX_OPPS, sizeof(*opps), GFP_KERNEL);
0399     if (!opps)
0400         return -ENOMEM;
0401 
0402     info->opps[cluster] = opps;
0403 
0404     off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE;
0405     for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) {
0406         ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
0407         if (!ret) {
0408             opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
0409             opps->u_volt = (data >> VOLT_SHIFT) * 1000;
0410         } else {
0411             break;
0412         }
0413     }
0414     info->num_opps[cluster] = idx;
0415 
0416     return ret;
0417 }
0418 
0419 static int ve_init_opp_table(struct device *cpu_dev)
0420 {
0421     int cluster;
0422     int idx, ret = 0, max_opp;
0423     struct ve_spc_opp *opps;
0424 
0425     cluster = topology_physical_package_id(cpu_dev->id);
0426     cluster = cluster < 0 ? 0 : cluster;
0427 
0428     max_opp = info->num_opps[cluster];
0429     opps = info->opps[cluster];
0430 
0431     for (idx = 0; idx < max_opp; idx++, opps++) {
0432         ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
0433         if (ret) {
0434             dev_warn(cpu_dev, "failed to add opp %lu %lu\n",
0435                  opps->freq, opps->u_volt);
0436             return ret;
0437         }
0438     }
0439     return ret;
0440 }
0441 
0442 int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq)
0443 {
0444     int ret;
0445     info = kzalloc(sizeof(*info), GFP_KERNEL);
0446     if (!info)
0447         return -ENOMEM;
0448 
0449     info->baseaddr = baseaddr;
0450     info->a15_clusid = a15_clusid;
0451 
0452     if (irq <= 0) {
0453         pr_err(SPCLOG "Invalid IRQ %d\n", irq);
0454         kfree(info);
0455         return -EINVAL;
0456     }
0457 
0458     init_completion(&info->done);
0459 
0460     readl_relaxed(info->baseaddr + PWC_STATUS);
0461 
0462     ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH
0463                 | IRQF_ONESHOT, "vexpress-spc", info);
0464     if (ret) {
0465         pr_err(SPCLOG "IRQ %d request failed\n", irq);
0466         kfree(info);
0467         return -ENODEV;
0468     }
0469 
0470     sema_init(&info->sem, 1);
0471     /*
0472      * Multi-cluster systems may need this data when non-coherent, during
0473      * cluster power-up/power-down. Make sure driver info reaches main
0474      * memory.
0475      */
0476     sync_cache_w(info);
0477     sync_cache_w(&info);
0478 
0479     return 0;
0480 }
0481 
0482 struct clk_spc {
0483     struct clk_hw hw;
0484     int cluster;
0485 };
0486 
0487 #define to_clk_spc(spc) container_of(spc, struct clk_spc, hw)
0488 static unsigned long spc_recalc_rate(struct clk_hw *hw,
0489         unsigned long parent_rate)
0490 {
0491     struct clk_spc *spc = to_clk_spc(hw);
0492     u32 freq;
0493 
0494     if (ve_spc_get_performance(spc->cluster, &freq))
0495         return -EIO;
0496 
0497     return freq * 1000;
0498 }
0499 
0500 static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
0501         unsigned long *parent_rate)
0502 {
0503     struct clk_spc *spc = to_clk_spc(hw);
0504 
0505     return ve_spc_round_performance(spc->cluster, drate);
0506 }
0507 
0508 static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
0509         unsigned long parent_rate)
0510 {
0511     struct clk_spc *spc = to_clk_spc(hw);
0512 
0513     return ve_spc_set_performance(spc->cluster, rate / 1000);
0514 }
0515 
0516 static struct clk_ops clk_spc_ops = {
0517     .recalc_rate = spc_recalc_rate,
0518     .round_rate = spc_round_rate,
0519     .set_rate = spc_set_rate,
0520 };
0521 
0522 static struct clk *ve_spc_clk_register(struct device *cpu_dev)
0523 {
0524     struct clk_init_data init;
0525     struct clk_spc *spc;
0526 
0527     spc = kzalloc(sizeof(*spc), GFP_KERNEL);
0528     if (!spc)
0529         return ERR_PTR(-ENOMEM);
0530 
0531     spc->hw.init = &init;
0532     spc->cluster = topology_physical_package_id(cpu_dev->id);
0533 
0534     spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
0535 
0536     init.name = dev_name(cpu_dev);
0537     init.ops = &clk_spc_ops;
0538     init.flags = CLK_GET_RATE_NOCACHE;
0539     init.num_parents = 0;
0540 
0541     return devm_clk_register(cpu_dev, &spc->hw);
0542 }
0543 
0544 static int __init ve_spc_clk_init(void)
0545 {
0546     int cpu, cluster;
0547     struct clk *clk;
0548     bool init_opp_table[MAX_CLUSTERS] = { false };
0549 
0550     if (!info)
0551         return 0; /* Continue only if SPC is initialised */
0552 
0553     if (ve_spc_populate_opps(0) || ve_spc_populate_opps(1)) {
0554         pr_err("failed to build OPP table\n");
0555         return -ENODEV;
0556     }
0557 
0558     for_each_possible_cpu(cpu) {
0559         struct device *cpu_dev = get_cpu_device(cpu);
0560         if (!cpu_dev) {
0561             pr_warn("failed to get cpu%d device\n", cpu);
0562             continue;
0563         }
0564         clk = ve_spc_clk_register(cpu_dev);
0565         if (IS_ERR(clk)) {
0566             pr_warn("failed to register cpu%d clock\n", cpu);
0567             continue;
0568         }
0569         if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
0570             pr_warn("failed to register cpu%d clock lookup\n", cpu);
0571             continue;
0572         }
0573 
0574         cluster = topology_physical_package_id(cpu_dev->id);
0575         if (cluster < 0 || init_opp_table[cluster])
0576             continue;
0577 
0578         if (ve_init_opp_table(cpu_dev))
0579             pr_warn("failed to initialise cpu%d opp table\n", cpu);
0580         else if (dev_pm_opp_set_sharing_cpus(cpu_dev,
0581              topology_core_cpumask(cpu_dev->id)))
0582             pr_warn("failed to mark OPPs shared for cpu%d\n", cpu);
0583         else
0584             init_opp_table[cluster] = true;
0585     }
0586 
0587     platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0);
0588     return 0;
0589 }
0590 device_initcall(ve_spc_clk_init);
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