arm/mach-versatile/integrator_ap.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
0004  */
0005 #include <linux/kernel.h>
0006 #include <linux/init.h>
0007 #include <linux/syscore_ops.h>
0008 #include <linux/amba/bus.h>
0009 #include <linux/io.h>
0010 #include <linux/irqchip.h>
0011 #include <linux/of_irq.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/termios.h>
0015 #include <linux/mfd/syscon.h>
0016 #include <linux/regmap.h>
0017
0018 #include <asm/mach/arch.h>
0019 #include <asm/mach/map.h>
0020
0021 #include "integrator-hardware.h"
0022 #include "integrator-cm.h"
0023 #include "integrator.h"
0024
0025 /* Regmap to the AP system controller */
0026 static struct regmap *ap_syscon_map;
0027
0028 /*
0029  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
0030  * is the (PA >> 12).
0031  *
0032  * Setup a VA for the Integrator interrupt controller (for header #0,
0033  * just for now).
0034  */
0035 #define VA_IC_BASE  __io_address(INTEGRATOR_IC_BASE)
0036
0037 /*
0038  * Logical      Physical
0039  * f1400000 14000000    Interrupt controller
0040  * f1600000 16000000    UART 0
0041  */
0042
0043 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
0044     {
0045         .virtual    = IO_ADDRESS(INTEGRATOR_IC_BASE),
0046         .pfn        = __phys_to_pfn(INTEGRATOR_IC_BASE),
0047         .length     = SZ_4K,
0048         .type       = MT_DEVICE
0049     }, {
0050         .virtual    = IO_ADDRESS(INTEGRATOR_UART0_BASE),
0051         .pfn        = __phys_to_pfn(INTEGRATOR_UART0_BASE),
0052         .length     = SZ_4K,
0053         .type       = MT_DEVICE
0054     }
0055 };
0056
0057 static void __init ap_map_io(void)
0058 {
0059     iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
0060 }
0061
0062 #ifdef CONFIG_PM
0063 static unsigned long ic_irq_enable;
0064
0065 static int irq_suspend(void)
0066 {
0067     ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
0068     return 0;
0069 }
0070
0071 static void irq_resume(void)
0072 {
0073     /* disable all irq sources */
0074     cm_clear_irqs();
0075     writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
0076     writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
0077
0078     writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
0079 }
0080 #else
0081 #define irq_suspend NULL
0082 #define irq_resume NULL
0083 #endif
0084
0085 static struct syscore_ops irq_syscore_ops = {
0086     .suspend    = irq_suspend,
0087     .resume     = irq_resume,
0088 };
0089
0090 static int __init irq_syscore_init(void)
0091 {
0092     register_syscore_ops(&irq_syscore_ops);
0093
0094     return 0;
0095 }
0096
0097 device_initcall(irq_syscore_init);
0098
0099 /*
0100  * For the PL010 found in the Integrator/AP some of the UART control is
0101  * implemented in the system controller and accessed using a callback
0102  * from the driver.
0103  */
0104 static void integrator_uart_set_mctrl(struct amba_device *dev,
0105                 void __iomem *base, unsigned int mctrl)
0106 {
0107     unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
0108     u32 phybase = dev->res.start;
0109     int ret;
0110
0111     if (phybase == INTEGRATOR_UART0_BASE) {
0112         /* UART0 */
0113         rts_mask = 1 << 4;
0114         dtr_mask = 1 << 5;
0115     } else {
0116         /* UART1 */
0117         rts_mask = 1 << 6;
0118         dtr_mask = 1 << 7;
0119     }
0120
0121     if (mctrl & TIOCM_RTS)
0122         ctrlc |= rts_mask;
0123     else
0124         ctrls |= rts_mask;
0125
0126     if (mctrl & TIOCM_DTR)
0127         ctrlc |= dtr_mask;
0128     else
0129         ctrls |= dtr_mask;
0130
0131     ret = regmap_write(ap_syscon_map,
0132                INTEGRATOR_SC_CTRLS_OFFSET,
0133                ctrls);
0134     if (ret)
0135         pr_err("MODEM: unable to write PL010 UART CTRLS\n");
0136
0137     ret = regmap_write(ap_syscon_map,
0138                INTEGRATOR_SC_CTRLC_OFFSET,
0139                ctrlc);
0140     if (ret)
0141         pr_err("MODEM: unable to write PL010 UART CRTLC\n");
0142 }
0143
0144 struct amba_pl010_data ap_uart_data = {
0145     .set_mctrl = integrator_uart_set_mctrl,
0146 };
0147
0148 static void __init ap_init_irq_of(void)
0149 {
0150     cm_init();
0151     irqchip_init();
0152 }
0153
0154 /* For the Device Tree, add in the UART callbacks as AUXDATA */
0155 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
0156     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
0157         "uart0", &ap_uart_data),
0158     OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
0159         "uart1", &ap_uart_data),
0160     { /* sentinel */ },
0161 };
0162
0163 static const struct of_device_id ap_syscon_match[] = {
0164     { .compatible = "arm,integrator-ap-syscon"},
0165     { },
0166 };
0167
0168 static void __init ap_init_of(void)
0169 {
0170     struct device_node *syscon;
0171
0172     of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
0173
0174     syscon = of_find_matching_node(NULL, ap_syscon_match);
0175     if (!syscon)
0176         return;
0177     ap_syscon_map = syscon_node_to_regmap(syscon);
0178     if (IS_ERR(ap_syscon_map)) {
0179         pr_crit("could not find Integrator/AP system controller\n");
0180         return;
0181     }
0182 }
0183
0184 static const char * ap_dt_board_compat[] = {
0185     "arm,integrator-ap",
0186     NULL,
0187 };
0188
0189 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
0190     .reserve    = integrator_reserve,
0191     .map_io     = ap_map_io,
0192     .init_irq   = ap_init_irq_of,
0193     .init_machine   = ap_init_of,
0194     .dt_compat      = ap_dt_board_compat,
0195 MACHINE_END